Visible to Intel only — GUID: byl1520431203992
Ixiasoft
Visible to Intel only — GUID: byl1520431203992
Ixiasoft
2.7.4.2. Pin Assignments
When you integrate your E-Tile Hard IP for Ethernet Intel® FPGA IP core instance in your design, you must make appropriate pin assignments. You can create a virtual pin to avoid making specific pin assignments for top-level signals until you are ready to map the design to hardware.
Stratix® 10 E-tile devices offer four instances of the hard IP on each E-Tile. Each instance offers one 100G channel and six 10G/25G channels. Your design must not include pin assignments that conflict with its location. In devices with multiple E-Tiles, you can specify the E-Tile to which the Ethernet link serial pins should map.