3.10.1. Clock Signals

E-Tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

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Date 7/23/2024

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3.10.1. Clock Signals

Each CPRI PHY channel has its own pair of datapath clocks and each transceiver has its own reference clock.

Table 93. CPRI PHY Clock Input Signals
Signal Name	Width (Bits)	I/O Direction	Description
`i_sl_clk_tx[n]`	1	Input	Single lane transmit datapath clock. These clocks drive the internal TX datapath for the CPRI PHY channel. Each CPRI PHY channel has its own clock input. The default frequency value is 402.8320 MHz.
`i_sl_clk_rx[n]`	1	Input	Single lane receive datapath clock. These clocks drive the internal RX datapath for the CPRI PHY channel. Each CPRI PHY channel has its own clock input. The default frequency value is 402.8320 MHz.
`i_clk_ref`	5	Input	Transceiver reference clock for each channel. An input multiplexer that supports five reference clocks. The default clock is index 0. You can select only 1 clock at any one time for a given channel. You can switch the clock through the transceiver reconfiguration interface. Use a 184.32 MHz reference clock to generate the high speed serial clock and datapath parallel clocks for CPRI line rates 10.1 and 24.3 Gbps with and without RS-FEC. Use a 153.6 MHz transceiver reference clock for CPRI line rates 2.4/3.0/4.9/6.1/9.8 Gbps.
`i_aib_clk`	1	Input	Clock for application interface block (AIB). This clock drives the AIB interface across all channels. The default frequency value is 402.8320 MHz.
`i_aib_x2_clk`	1	Input	Double frequency clock for AIB from external source. This clock also drives the AIB interface across all channels. The default frequency value is 805.6640 MHz.
`i_reconfig_clk`	1	Input	Reconfiguration clock. Frequency of 100 MHz for CSR access on all the Avalon® memory-mapped interfaces.
`i_sampling_clk`	1	Input	Sampling clock for deterministic latency logic. The default frequency value is 250 MHz.

Table 94. Clock Source SignalsLists the clock source ports for the CPRI core. The core provides locally generated PLL clocks and recovered clocks that can be used for the datapath.
Signal Name	Width (Bits)	I/O Direction	Description
`o_tx_clkout[n]`	1	Output	Parallel TX clock running at line rate/64.
`o_tx_clkout2[n]`	1	Output	Parallel TX clock running at line rate/66. This clock drives the active TX and RX MII interface for the CPRI PHY channel.
`o_rx_clkout[n]`	1	Output	Parallel RX recovered clock running at line rate/64.
`o_rx_clkout2[n]`	1	Output	Parallel RX recovered clock running at line rate/66.

Table 95. Clock Status SignalsLists the clock status ports for the CPRI core. Use these ports to hold the circuits that use clock sources from the core in reset until the PLLs driving the clocks are locked.
Signal Name	Width	I/O Direction	Description
`o_tx_pll_locked[n]`	1	Output	Indicates the TX PLL driving clock signals from the core is locked. Altera recommends not to use the `o_tx_clkout` or `o_tx_clkout2` clocks until the `o_tx_pll_locked` clock is high.
`o_cdr_lock[n]`	1	Output	Indicates that the recovered clocks are locked to data. Altera recommends not to use the `o_rx_clkout` or `o_rx_clkout2` clocks until the `o_cdr_lock` clock is high.