Visible to Intel only — GUID: wpl1555595244708
Ixiasoft
Visible to Intel only — GUID: wpl1555595244708
Ixiasoft
2.11.17.3.5. 10G/25G Ethernet Channel with Basic PTP Accuracy Mode
When PTP is enabled, the external AIB clocking is inherently enabled. Do not enable External AIB clocking parameter in the Parameter Editor, it is unnecessary and redundant. In the Quartus® Prime Pro Edition software version 21.4 or later, the Enable external AIB clocking parameter is not available when the Enable IEEE 1588 PTP parameter is turned on.
Number of Ethernet Channels | Data Rate | Core Interface | External AIB Clocking |
---|---|---|---|
2 | 25.78125 Gbps | 64 bits | Disabled |
This use case covers a scenario when PTP is enabled and the PTP Accuracy Mode is set to Basic Mode.
With PTP enabled, a PTP channel and its source clock called PTP clock becomes the master channel regardless of FEC configuration.
Number of Channels of 10G/25G | Clock Port | PTP Clock | Clock Connection Guideline |
---|---|---|---|
Single channel | i_sl_clk_tx i_sl_clk_rx |
o_clk_pll_div64[1] |
Connect o_clk_pll_div64[1] to i_sl_clk_tx and i_sl_clk_rx. |
2 channels | i_sl_clk_tx[1:0] i_sl_clk_rx[1:0] |
o_clk_pll_div64[2] | Connect o_clk_pll_div64[2] to i_sl_clk_tx[1:0] and i_sl_clk_rx[1:0]. |
3 channels | i_sl_clk_tx[2:0] i_sl_clk_rx[2:0] |
o_clk_pll_div64[3] | Connect o_clk_pll_div64[3] to i_sl_clk_tx[2:0] and i_sl_clk_rx[2:0]. |
4 channels | i_sl_clk_tx[3:0] i_sl_clk_rx[3:0] |
o_clk_pll_div64[4] | Connect o_clk_pll_div64[4] to i_sl_clk_tx[3:0] and i_sl_clk_rx[3:0]. |