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1. About the Drive-On-Chip Design Example for Cyclone V Devices
2. Motor Control Boards
3. Drive-On-Chip Design Example for Cyclone V Devices Features
4. Getting Started
5. Building the Design
6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console
7. About the Scaling of Feedback Signals
8. Motor Control Software
9. Functional Description of the Drive-On-Chip Design Example
10. Achieving Timing Closure on a Motor Control Design
11. Design Security Recommendations
12. Reference Documents for the Drive-on-Chip Design Example
13. Document Revision History for AN 669: Drive-on-Chip Reference Design
4.1. Software Requirements for the Drive-On-Chip Design Example for Cyclone V Devices
4.2. Downloading and Installing the Drive-On-Chip Design Example for Cyclone V Devices
4.3. Setting Up the Motor Control Board with your Development Board
4.4. Programming the Hardware onto the Device
4.5. Setting Up Terminal Emulator
4.6. Downloading the HPS Software to the Device
6.1. System Console GUI Upper Pane for the Drive-On-Chip Design Example
6.2. System Console GUI Lower Pane for the Drive-On-Chip Design Example
6.3. Vibration Suppression Tab
6.4. Controlling the DC-DC Converter
6.5. Tuning the PI Controller Gains
6.6. Controlling the Speed and Position Demonstrations
6.7. Monitoring Performance
9.1. Processor Subsystem
9.2. Six-channel PWM Interface
9.3. DC Link Monitor
9.4. Drive System Monitor
9.5. Quadrature Encoder Interface
9.6. Sigma-Delta ADC Interface for Drive Axes
9.7. DC-DC Converter
9.8. Motor Control Modes
9.9. FOC Subsystem
9.10. FFTs
9.11. DEKF Technique for Battery Management
9.12. Signals
9.13. Registers
9.9.1. DSP Builder for Intel FPGAs Model for the Drive-On-Chip Designs
9.9.2. Avalon Memory-Mapped Interface
9.9.3. About DSP Builder for Intel FPGAs
9.9.4. DSP Builder for Intel FPGAs Folding
9.9.5. DSP Builder for Intel FPGAs Model Resource Usage
9.9.6. DSP Builder for Intel FPGAs Design Guidelines
9.9.7. Generating VHDL for the DSP Builder Models for the Drive-On-Chip Reference Designs
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9.2. Six-channel PWM Interface
The Drive-On-Chip Design Example six-channel PWM interface operates as three pairs of outputs, with each driving the upper and lower power transistors (e.g., MOSFET driven via external drivers) in a half-bridge power stage.
The PWM interface operates with a PWM carrier clock of 300 MHz for high resolution control of the MOSFET switching times.
The PWM interface ensures a dead time between switching to ensure both outputs are not high at the same time; the dead time prevents short circuit “shoot-through” in the power transistors. The input clock and a PWM counter set the PWM frequency. The counter alternately ramps up from zero to a maximum value and ramps down from the maximum value to zero. The sequence is as follows:
0, 1, 2, …, max - 1, max, max - 1, …, 2, 1, 0, …
Figure 30. PWM Counter Value
The maximum value of the counter ramp, max, is software configurable. The PWM frequency is fPWM = fCLK/(2 x max)
The design generates high- and low-side drive signals for the MOSFET module by comparing the ramp counter value with the values you set in the PWM threshold configuration registers. The design inserts a dead period between the switching of the upper and lower drive signals according to the value set in the PWM blocking time configuration register.
The design sets carrier_latch output signal high for one clock cycle when the PWM counter is at 0 or max. This signal triggers a position encoder to take a position reading.
Based on the PWM counter value, the PWM component generates configurable timing output strobes for triggering ADC conversion for feedback-current readings. Configure the ADC start pulse to perform the conversion during the quietest period of the PWM cycle away from PWM switching events (around the min and max values of the PWM counter).
The start output signal is a trigger for the ADC IP to start conversion. The trigger_up configuration register sets the PWM count value and the start signal is high for one clock cycle while the PWM is counting up. The trigger_down configuration register sets the PWM count value and the start signal is high for one clock cycle while the PWM is counting down. Set the trigger_up and trigger_down registers symmetrically to ensure a regular ADC sample position offset before the reversal point of the counter. In other words, trigger_up = MAX - offset, and trigger_down = offset.
The design calculates the PWM blocking time configuration register as pwm_block = dead time x fCLK. Dead time refers to the time when the design turns off both upper and lower transistors, to prevent short circuits. You must obtain specific dead time values for the specific MOSFET module you are using. For example, with a dead time requirement of 2μs and a PWM module clock of 300 MHz, the pwm_block value is 600 (=2μs x 300 MHz. Figure 5 shows PWM output generation (including dead time).
Figure 31. PWM Output Generation (Including Dead Time)
Figure 32. Configurable Timing Output Strobes