AN 669: Drive-On-Chip Design Example for Cyclone V Devices

Download PDF
ID 683466
Date 5/15/2022
Public
Document Table of Contents
Document Table of Contents x
1. About the Drive-On-Chip Design Example for Cyclone V Devices 2. Motor Control Boards 3. Drive-On-Chip Design Example for Cyclone V Devices Features 4. Getting Started 5. Building the Design 6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console 7. About the Scaling of Feedback Signals 8. Motor Control Software 9. Functional Description of the Drive-On-Chip Design Example 10. Achieving Timing Closure on a Motor Control Design 11. Design Security Recommendations 12. Reference Documents for the Drive-on-Chip Design Example 13. Document Revision History for AN 669: Drive-on-Chip Reference Design
4. Getting Started x
4.1. Software Requirements for the Drive-On-Chip Design Example for Cyclone V Devices 4.2. Downloading and Installing the Drive-On-Chip Design Example for Cyclone V Devices 4.3. Setting Up the Motor Control Board with your Development Board 4.4. Programming the Hardware onto the Device 4.5. Setting Up Terminal Emulator 4.6. Downloading the HPS Software to the Device
4.6. Downloading the HPS Software to the Device x
4.6.1. Downloading the HPS Software with the Arm GUI 4.6.2. Downloading the HPS Software with the Arm Script
5. Building the Design x
5.1. Compiling the Drive-on-Chip Design Example 5.2. Preparing the µC/OS-II HPS Software Files 5.3. Compiling the µC/OS-II HPS Software 5.4. Creating and Booting an HPS SD Card Software Image 5.5. Creating and Booting a SD Card with both Software Image and Hardware Image
5.3. Compiling the µC/OS-II HPS Software x
5.3.1. Compiling the µC/OS-II HPS Software with the Arm GUI 5.3.2. Compiling the µC/OS-II HPS Software with the Arm Script
6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console x
6.1. System Console GUI Upper Pane for the Drive-On-Chip Design Example 6.2. System Console GUI Lower Pane for the Drive-On-Chip Design Example 6.3. Vibration Suppression Tab 6.4. Controlling the DC-DC Converter 6.5. Tuning the PI Controller Gains 6.6. Controlling the Speed and Position Demonstrations 6.7. Monitoring Performance
6.3. Vibration Suppression Tab x
6.3.1. About the Demonstration 6.3.2. Starting the Demonstration 6.3.3. FFT0 and FFT1 Graphs 6.3.4. Setting Up FFT 6.3.5. Setting Up Command Waveform 6.3.6. Setting Up Second Order IIR Filter
7. About the Scaling of Feedback Signals x
7.1. Signal Sensing in Sigma-Delta ADCs 7.2. Signal Scaling in the Software of the Drive-On-Chip Design Example 7.3. Scale Factors for the Drive-On-Chip Design Example in the System Console Toolkit
8. Motor Control Software x
8.1. Viewing Motor Control Software Help Files 8.2. Software Application Configuration Files 8.3. Defining a New Motor or Encoder Type 8.4. SoC HPS Motor Control Software Project 8.5. Building the HPS Preloader
9. Functional Description of the Drive-On-Chip Design Example x
9.1. Processor Subsystem 9.2. Six-channel PWM Interface 9.3. DC Link Monitor 9.4. Drive System Monitor 9.5. Quadrature Encoder Interface 9.6. Sigma-Delta ADC Interface for Drive Axes 9.7. DC-DC Converter 9.8. Motor Control Modes 9.9. FOC Subsystem 9.10. FFTs 9.11. DEKF Technique for Battery Management 9.12. Signals 9.13. Registers
9.4. Drive System Monitor x
9.4.1. Drive System Monitor States for the Drive-On-Chip Design Example
9.6. Sigma-Delta ADC Interface for Drive Axes x
9.6.1. Offset Adjustment for Sigma-Delta ADC Interface
9.7. DC-DC Converter x
9.7.1. DC-DC Control Simulink Models 9.7.2. Sigma-Delta ADC Interface for DC-DC Converter
9.7.1. DC-DC Control Simulink Models x
9.7.1.1. DC-DC Control Block 9.7.1.2. Generating VHDL for the DSP Builder for Intel FPGAs Models for the DC-DC Converter
9.7.1.1. DC-DC Control Block x
9.7.1.1.1. DC-DC Model and VHDL Entity Signal Names and Data Format
9.9. FOC Subsystem x
9.9.1. DSP Builder for Intel FPGAs Model for the Drive-On-Chip Designs 9.9.2. Avalon Memory-Mapped Interface 9.9.3. About DSP Builder for Intel FPGAs 9.9.4. DSP Builder for Intel FPGAs Folding 9.9.5. DSP Builder for Intel FPGAs Model Resource Usage 9.9.6. DSP Builder for Intel FPGAs Design Guidelines 9.9.7. Generating VHDL for the DSP Builder Models for the Drive-On-Chip Reference Designs
9.10. FFTs x
9.10.1. Servo FFTs 9.10.2. Vibration Suppression 9.10.3. Command Waveform 9.10.4. IIR Filter 9.10.5. IIR Filter Tuning Parameters 9.10.6. IIR Filter Examples 9.10.7. Vibration Detection
9.10.1. Servo FFTs x
9.10.1.1. Running test_servofft.mdl
10. Achieving Timing Closure on a Motor Control Design x
10.1. Optimizing Motor Control Designs
1. About the Drive-On-Chip Design Example for Cyclone V Devices
2. Motor Control Boards
3. Drive-On-Chip Design Example for Cyclone V Devices Features
4. Getting Started
5. Building the Design
6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console
7. About the Scaling of Feedback Signals
8. Motor Control Software
9. Functional Description of the Drive-On-Chip Design Example
10. Achieving Timing Closure on a Motor Control Design
11. Design Security Recommendations
12. Reference Documents for the Drive-on-Chip Design Example
13. Document Revision History for AN 669: Drive-on-Chip Reference Design

4.6.1. Downloading the HPS Software with the Arm GUI

You must have an Arm Development Studio license to download the HPS software. Alternatively you can download the software with the Arm script.
  1. Run SoC EDS command shell by typing the following command:
    "<your_ArmDS_install_path_in_Cygwin_expresstion>/bin/cmdsuite.exe"
    For example: "/cygdrive/c/Program\ Files/Arm/Development\ Studio\ 2021.1/bin/cmdsuite.exe"
  2. Type the following command in the SoC EDS command shell:
    "armds_ide&"
    The Arm Development Studio IDE Launcher opens.
  3. Browse to <project_dir>/software, click Select Folder, then click Launch.
  4. Select Run > Debug Configurations.
    Figure 4. Connection Tab
  5. Create a new debugger configuration by double clicking Generic Arm C/C++ Application
  6. On the Connection tab, select Debug Cortex-A9_0 under Intel SoC FPGA|Cyclone V SoC (Dual Core)|Bare Metal Debug.
  7. In the Target Connection drop-down select USB-Blaster and for Clock speed select 20MHz.
  8. In the Bare Metal Debug Connection field, click Browse… and select the USB Blaster II on localhost.
  9. Select the Debugger tab.
  10. In Run Control, select Connect Only.
  11. Turn on Run debug initialization debugger script (.ds / .py).
  12. Click File system to select the following file <project_dir>\software\DOC_TANDEM_CVSX\src\DriveOnChip\debug.ds, then click Open.
  13. In Host working directory turn on Use default .
  14. Click Apply to save the configuration, optionally specifying a name for the new configuration.
  15. Click Debug.
  16. Click Continue in the Debug Control panel to run the application.
  17. Check that the terminal console display shows the correct FPGA and power board combination. For example: 
    [DECODE SYSID] Decoding hardware platform from QSYS SYSID data : 0x004042FE
[DECODE SYSID] SYSID_VERSION_MAJOR : 0x04
[DECODE SYSID] SYSID_VERSION_MINOR : 0x00
[DECODE SYSID] SYSID_POWERBOARD_ID : 0x04
[DECODE SYSID] SYSID_DEVICE_FAMILY : 0x02
[DECODE SYSID] SYSID_DESIGN_ID     : 0xFE
[DECODE SYSID] Hardware design version: 4.0
[DECODE SYSID] FPGA Board     : Cyclone V SX Dev Kit
[DECODE SYSID] Power Board    : Intel Tandem Motion Power
[DECODE SYSID] Power board has 2 axes available
[DECODE SYSID] Axis 0         : Enabled
[DECODE SYSID] Axis 1         : Enabled
  18. Apply power to the power board when you see the following message in the terminal console:
    ---> DC input voltage error - Check power connection
    The motor starts to turn.
  19. When the application is running, right-click on Cortex-A9_0 and click Disconnect from Target.
Level Two Title