AN 669: Drive-On-Chip Design Example for Cyclone V Devices

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ID 683466
Date 5/15/2022
Public
Document Table of Contents
Document Table of Contents x
1. About the Drive-On-Chip Design Example for Cyclone V Devices 2. Motor Control Boards 3. Drive-On-Chip Design Example for Cyclone V Devices Features 4. Getting Started 5. Building the Design 6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console 7. About the Scaling of Feedback Signals 8. Motor Control Software 9. Functional Description of the Drive-On-Chip Design Example 10. Achieving Timing Closure on a Motor Control Design 11. Design Security Recommendations 12. Reference Documents for the Drive-on-Chip Design Example 13. Document Revision History for AN 669: Drive-on-Chip Reference Design
4. Getting Started x
4.1. Software Requirements for the Drive-On-Chip Design Example for Cyclone V Devices 4.2. Downloading and Installing the Drive-On-Chip Design Example for Cyclone V Devices 4.3. Setting Up the Motor Control Board with your Development Board 4.4. Programming the Hardware onto the Device 4.5. Setting Up Terminal Emulator 4.6. Downloading the HPS Software to the Device
4.6. Downloading the HPS Software to the Device x
4.6.1. Downloading the HPS Software with the Arm GUI 4.6.2. Downloading the HPS Software with the Arm Script
5. Building the Design x
5.1. Compiling the Drive-on-Chip Design Example 5.2. Preparing the µC/OS-II HPS Software Files 5.3. Compiling the µC/OS-II HPS Software 5.4. Creating and Booting an HPS SD Card Software Image 5.5. Creating and Booting a SD Card with both Software Image and Hardware Image
5.3. Compiling the µC/OS-II HPS Software x
5.3.1. Compiling the µC/OS-II HPS Software with the Arm GUI 5.3.2. Compiling the µC/OS-II HPS Software with the Arm Script
6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console x
6.1. System Console GUI Upper Pane for the Drive-On-Chip Design Example 6.2. System Console GUI Lower Pane for the Drive-On-Chip Design Example 6.3. Vibration Suppression Tab 6.4. Controlling the DC-DC Converter 6.5. Tuning the PI Controller Gains 6.6. Controlling the Speed and Position Demonstrations 6.7. Monitoring Performance
6.3. Vibration Suppression Tab x
6.3.1. About the Demonstration 6.3.2. Starting the Demonstration 6.3.3. FFT0 and FFT1 Graphs 6.3.4. Setting Up FFT 6.3.5. Setting Up Command Waveform 6.3.6. Setting Up Second Order IIR Filter
7. About the Scaling of Feedback Signals x
7.1. Signal Sensing in Sigma-Delta ADCs 7.2. Signal Scaling in the Software of the Drive-On-Chip Design Example 7.3. Scale Factors for the Drive-On-Chip Design Example in the System Console Toolkit
8. Motor Control Software x
8.1. Viewing Motor Control Software Help Files 8.2. Software Application Configuration Files 8.3. Defining a New Motor or Encoder Type 8.4. SoC HPS Motor Control Software Project 8.5. Building the HPS Preloader
9. Functional Description of the Drive-On-Chip Design Example x
9.1. Processor Subsystem 9.2. Six-channel PWM Interface 9.3. DC Link Monitor 9.4. Drive System Monitor 9.5. Quadrature Encoder Interface 9.6. Sigma-Delta ADC Interface for Drive Axes 9.7. DC-DC Converter 9.8. Motor Control Modes 9.9. FOC Subsystem 9.10. FFTs 9.11. DEKF Technique for Battery Management 9.12. Signals 9.13. Registers
9.4. Drive System Monitor x
9.4.1. Drive System Monitor States for the Drive-On-Chip Design Example
9.6. Sigma-Delta ADC Interface for Drive Axes x
9.6.1. Offset Adjustment for Sigma-Delta ADC Interface
9.7. DC-DC Converter x
9.7.1. DC-DC Control Simulink Models 9.7.2. Sigma-Delta ADC Interface for DC-DC Converter
9.7.1. DC-DC Control Simulink Models x
9.7.1.1. DC-DC Control Block 9.7.1.2. Generating VHDL for the DSP Builder for Intel FPGAs Models for the DC-DC Converter
9.7.1.1. DC-DC Control Block x
9.7.1.1.1. DC-DC Model and VHDL Entity Signal Names and Data Format
9.9. FOC Subsystem x
9.9.1. DSP Builder for Intel FPGAs Model for the Drive-On-Chip Designs 9.9.2. Avalon Memory-Mapped Interface 9.9.3. About DSP Builder for Intel FPGAs 9.9.4. DSP Builder for Intel FPGAs Folding 9.9.5. DSP Builder for Intel FPGAs Model Resource Usage 9.9.6. DSP Builder for Intel FPGAs Design Guidelines 9.9.7. Generating VHDL for the DSP Builder Models for the Drive-On-Chip Reference Designs
9.10. FFTs x
9.10.1. Servo FFTs 9.10.2. Vibration Suppression 9.10.3. Command Waveform 9.10.4. IIR Filter 9.10.5. IIR Filter Tuning Parameters 9.10.6. IIR Filter Examples 9.10.7. Vibration Detection
9.10.1. Servo FFTs x
9.10.1.1. Running test_servofft.mdl
10. Achieving Timing Closure on a Motor Control Design x
10.1. Optimizing Motor Control Designs
1. About the Drive-On-Chip Design Example for Cyclone V Devices
2. Motor Control Boards
3. Drive-On-Chip Design Example for Cyclone V Devices Features
4. Getting Started
5. Building the Design
6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console
7. About the Scaling of Feedback Signals
8. Motor Control Software
9. Functional Description of the Drive-On-Chip Design Example
10. Achieving Timing Closure on a Motor Control Design
11. Design Security Recommendations
12. Reference Documents for the Drive-on-Chip Design Example
13. Document Revision History for AN 669: Drive-on-Chip Reference Design

7.1. Signal Sensing in Sigma-Delta ADCs

Sigma-delta modulators on the power board convert analog signals to a one-wire digital bitstream. The design demodulates or filters the bitstream in the FPGA. The FPGA uses several types of sigma-delta filter IP in the FPGA, ADC modules and DC link modules, each with different scaling and offset.

The design downloads and filters all sigma delta inputs in parallel so no skew exists between the samples that it feeds to the software application.

Each ADC type has a different input ranges. The corresponding 'C' data type is 16-bit integer.

Table 6.  ADC Output Data
ADC Type Input Range Count Range C Data type
Sigma-delta ADC -320…+320mV -32768…+32767 Signed 16-bit
Sigma-delta DC link voltage 0…+320mV 0…+32767 Signed or unsigned 16-bit

Position feedback samples are scaled to a 23 bit unsigned integer, for consistency across all encoder types supported by this and previous Drive-On-Chip designs.

Table 7.  ADC ScalingThis table shows the ADC scaling for all signals, ADC type and board revision. The scaling depends on the way the power board processes the signals (e.g., value of current shunts, scaling, and offset in sense amplifiers).
Feedback Quantity Sigma Delta Interface IP Sigma Delta Scaling for Tandem Motion Power Board
Motor Phase Voltages ADC interface 545 counts/V
DC Bus Voltage ADC interface 40 counts/V
Input Voltage DC Link 895 counts/V
Input Current DC Link 256 counts/A
DC-DC Inductor Current ADC interface 717 counts/A
DC Bus Current DC Link 1638 counts/A
Motor Phase Currents ADC interface 1024 counts/A
Table 8.  ADC ScalingThis table shows the ADC scaling for all signals. The scaling depends on the way the power board processes the signals (e.g., value of current shunts, scaling, and offset in sense amplifiers) and filter IP scaling in FPGA. The design uses the DC Bus Voltage and DC-DC Inductor Current as feedback control for the DC-DC controller IP, but scales them differently for the DC-DC controller IP. The design performs the scaling in hardware. The table shows the scaling factor in the last column in the table. For more information, refer to DC-DC Control Block.
Feedback Quantity Sigma Delta Interface IP Scaling for Software Interface (Avalon Memory-mapped Registers) Scaling for DC-DC Controller Hardware IP
Motor Phase Voltages ADC interface in DOC_Axix_Periphs subsystem 545 counts/V N/A
Motor Phase Currents ADC interface in DOC_Axix_Periphs subsystem 1024 counts/A N/A
DC link Input Voltage DC Link Monitor in lvmc_dclink subsystem 895 counts/V N/A
DC link input Current DC Link Monitor in lvmc_dclink subsystem 256 counts/A N/A
DC link output (DC Bus) Current DC Link Monitor in lvmc_dclink subsystem 1638 counts/A N/A
DC link output (DC Bus) Voltage ADC interface in DC-DC Boost Converter 545 counts/V 40 counts/V
DC-DC Inductor Currents ADC interface in DC-DC Boost Converter 717 counts/A 100 counts/A
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