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1. About the Drive-On-Chip Design Example for Cyclone V Devices
2. Motor Control Boards
3. Drive-On-Chip Design Example for Cyclone V Devices Features
4. Getting Started
5. Building the Design
6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console
7. About the Scaling of Feedback Signals
8. Motor Control Software
9. Functional Description of the Drive-On-Chip Design Example
10. Achieving Timing Closure on a Motor Control Design
11. Design Security Recommendations
12. Reference Documents for the Drive-on-Chip Design Example
13. Document Revision History for AN 669: Drive-on-Chip Reference Design
4.1. Software Requirements for the Drive-On-Chip Design Example for Cyclone V Devices
4.2. Downloading and Installing the Drive-On-Chip Design Example for Cyclone V Devices
4.3. Setting Up the Motor Control Board with your Development Board
4.4. Programming the Hardware onto the Device
4.5. Setting Up Terminal Emulator
4.6. Downloading the HPS Software to the Device
6.1. System Console GUI Upper Pane for the Drive-On-Chip Design Example
6.2. System Console GUI Lower Pane for the Drive-On-Chip Design Example
6.3. Vibration Suppression Tab
6.4. Controlling the DC-DC Converter
6.5. Tuning the PI Controller Gains
6.6. Controlling the Speed and Position Demonstrations
6.7. Monitoring Performance
9.1. Processor Subsystem
9.2. Six-channel PWM Interface
9.3. DC Link Monitor
9.4. Drive System Monitor
9.5. Quadrature Encoder Interface
9.6. Sigma-Delta ADC Interface for Drive Axes
9.7. DC-DC Converter
9.8. Motor Control Modes
9.9. FOC Subsystem
9.10. FFTs
9.11. DEKF Technique for Battery Management
9.12. Signals
9.13. Registers
9.9.1. DSP Builder for Intel FPGAs Model for the Drive-On-Chip Designs
9.9.2. Avalon Memory-Mapped Interface
9.9.3. About DSP Builder for Intel FPGAs
9.9.4. DSP Builder for Intel FPGAs Folding
9.9.5. DSP Builder for Intel FPGAs Model Resource Usage
9.9.6. DSP Builder for Intel FPGAs Design Guidelines
9.9.7. Generating VHDL for the DSP Builder Models for the Drive-On-Chip Reference Designs
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9.9. FOC Subsystem
The Drive-On-Chip Design uses DSP Builder for Intel FPGAs to generate the HDL code for floating-point and fixed-point implementations of the field-oriented control (FOC) algorithm. The processor uses this DSP Builder-generated FOC IP as a coprocessor and moves the data between the FOC IP and the peripherals.
Note: Alternatively, the design includes software implementations of the FOC algorithm with the same FOC functionality. You can select which implementation to run using the Debug GUI. In all FOC implementations, the design performs the reverse Clarke transform as part of the SVM function in software.
FOC controls a motor's sinusoidal 3-phase currents in real time to create a smoothly rotating magnetic flux pattern, where the frequency of rotation corresponds to the frequency of the sine waves. FOC controls the current vector to keep:
- The torque-producing quadrature current, Iq, at 90 degrees to the rotor magnet flux axis
- The direct current component, Id, (commanded to be zero) inline with the rotor magnet flux.
The FOC algorithm:
- Converts the 3-phase feedback current inputs and the rotor position from the encoder into quadrature and direct current components using Clarke and Park transforms.
- Uses these current components as the inputs to two proportional and integral (PI) controllers running in parallel to adjust the direct current to zero and the quadrature current to the desired torque.
- Converts the direct and quadrature voltage outputs from the PI controllers back to 3-phase voltages with inverse Clarke and Park transforms.
The FOC algorithm includes:
- Forward and reverse Clarke and Park transforms
- Direct and quadrature current
- Proportional integral (PI) control loops
- Sine and cosine
- Saturate functions
Section Content
DSP Builder for Intel FPGAs Model for the Drive-On-Chip Designs
Avalon Memory-Mapped Interface
About DSP Builder for Intel FPGAs
DSP Builder for Intel FPGAs Folding
DSP Builder for Intel FPGAs Model Resource Usage
DSP Builder for Intel FPGAs Design Guidelines
Generating VHDL for the DSP Builder Models for the Drive-On-Chip Reference Designs