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1. About the Drive-On-Chip Design Example for Cyclone V Devices
2. Motor Control Boards
3. Drive-On-Chip Design Example for Cyclone V Devices Features
4. Getting Started
5. Building the Design
6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console
7. About the Scaling of Feedback Signals
8. Motor Control Software
9. Functional Description of the Drive-On-Chip Design Example
10. Achieving Timing Closure on a Motor Control Design
11. Design Security Recommendations
12. Reference Documents for the Drive-on-Chip Design Example
13. Document Revision History for AN 669: Drive-on-Chip Reference Design
4.1. Software Requirements for the Drive-On-Chip Design Example for Cyclone V Devices
4.2. Downloading and Installing the Drive-On-Chip Design Example for Cyclone V Devices
4.3. Setting Up the Motor Control Board with your Development Board
4.4. Programming the Hardware onto the Device
4.5. Setting Up Terminal Emulator
4.6. Downloading the HPS Software to the Device
6.1. System Console GUI Upper Pane for the Drive-On-Chip Design Example
6.2. System Console GUI Lower Pane for the Drive-On-Chip Design Example
6.3. Vibration Suppression Tab
6.4. Controlling the DC-DC Converter
6.5. Tuning the PI Controller Gains
6.6. Controlling the Speed and Position Demonstrations
6.7. Monitoring Performance
9.1. Processor Subsystem
9.2. Six-channel PWM Interface
9.3. DC Link Monitor
9.4. Drive System Monitor
9.5. Quadrature Encoder Interface
9.6. Sigma-Delta ADC Interface for Drive Axes
9.7. DC-DC Converter
9.8. Motor Control Modes
9.9. FOC Subsystem
9.10. FFTs
9.11. DEKF Technique for Battery Management
9.12. Signals
9.13. Registers
9.9.1. DSP Builder for Intel FPGAs Model for the Drive-On-Chip Designs
9.9.2. Avalon Memory-Mapped Interface
9.9.3. About DSP Builder for Intel FPGAs
9.9.4. DSP Builder for Intel FPGAs Folding
9.9.5. DSP Builder for Intel FPGAs Model Resource Usage
9.9.6. DSP Builder for Intel FPGAs Design Guidelines
9.9.7. Generating VHDL for the DSP Builder Models for the Drive-On-Chip Reference Designs
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9.7.1.1. DC-DC Control Block
The Drive-On-Chip Design Example DC-DC Converter block contains a DC-DC Control block, which is implemented in a DSP Builder for Intel FPGAs model (lvdcdc_adsp_vhdl.slx)
The DC-DC control block consists of
- Fault latches block
- PI controller block
- Two independent current control loops
- Voltage control loop
- PWM block
Figure 38. DSP Builder for Intel FPGAs DC-DC Control Block The figure shows the expanded DC-DC Control block
The DC-DC control block has the portion of the simulation for which you generate VHDL code. The ChannelIn and ChannelOut blocks are the port interface for the VHDL code. The MATLAB Simulink* inport and output signals define the VHDL signal names, and the VHDL data formats are the signal formats that you typically set with the Convert block.
The Convert DSP block sets the data format. This model uses signed-fractional data format for the feedback signals and the control math inside the DC-DC Control block.
For instance, the voltage feedback signal voltage_fdbk comes into the DC-DC Control block with data format sfix13 and scaling “2^0” (“13bits . 0bits”, where 13bits includes sign bit), which matches the 12 bit ADC twos-complement format. DSP Builder for Intel FPGAs also uses twos-complement maths to perform any calculations.
After the signal voltage_fdbk is inside the DC-DC control block the resolution is increased with another convert block to “sfix(27)” with output scaling “2^-12” (“15bits . 12bits").
In the PWM block, the design generates a triangular wave bounded within [-1.1] using a SR latch and counter counting at the frequency of the system clock of 20 MHz. After every 10000/freq_khz steps, the counter changes the direction of up-down counting. The design compares the triangular signal with thresholds representing the PWM duty cycle commands bounded within [-0.9, 0.9] to produce pulses for driving gates for each phase. The design inserts dead-time of ten samples time duration (for clk=20 MHz) at every transition of gate driving signals. You can extend the dead time by increasing the number of sample delays.
If the design asserts the fault input to the DC-DC converter, the enable bit in the DC-DC converter’s control register is cleared and the DC-DC converter turns off. The enable bit remains cleared, and writing to the control register cannot set it again until the system negates the fault input.
The port map for the DSP Builder for Intel FPGAs-generated VHDL entity is:
entity lvdcdc_adsp_vhdl_DC_DC_Control is
port (
in1 : in std_logic_vector(0 downto 0); -- ufix1
in2 : in std_logic_vector(7 downto 0); -- ufix8
CMD_DC_in : in std_logic_vector(13 downto 0); -- ufix14
voltage_fdbk : in std_logic_vector(12 downto 0); -- sfix13
current_fdbk_a : in std_logic_vector(12 downto 0); -- sfix13
current_fdbk_b : in std_logic_vector(12 downto 0); -- sfix13
freq_khz : in std_logic_vector(13 downto 0); -- ufix14
enable : in std_logic_vector(0 downto 0); -- ufix1
open_0_close_1 : in std_logic_vector(0 downto 0); -- ufix1
duty_0_100 : in std_logic_vector(13 downto 0); -- ufix14
pwm_sync_n : in std_logic_vector(0 downto 0); -- ufix1
pgain_voltage : in std_logic_vector(13 downto 0); -- ufix14
igain_voltage : in std_logic_vector(13 downto 0); -- ufix14
pgain_current : in std_logic_vector(13 downto 0); -- ufix14
igain_current : in std_logic_vector(13 downto 0); -- ufix14
bidir_en : in std_logic_vector(0 downto 0); -- ufix1
out1 : out std_logic_vector(0 downto 0); -- ufix1
out2 : out std_logic_vector(7 downto 0); -- ufix8
gate_a_l : out std_logic_vector(0 downto 0); -- ufix1
gate_a_h : out std_logic_vector(0 downto 0); -- ufix1
gate_b_l : out std_logic_vector(0 downto 0); -- ufix1
gate_b_h : out std_logic_vector(0 downto 0); -- ufix1
OV : out std_logic_vector(0 downto 0); -- ufix1
OC : out std_logic_vector(0 downto 0); -- ufix1
clk : in std_logic;
areset : in std_logic
);
end lvdcdc_adsp_vhdl_DC_DC_Control;