AN 669: Drive-On-Chip Design Example for Cyclone V Devices

Download PDF
ID 683466
Date 5/15/2022
Public
Document Table of Contents
Document Table of Contents x
1. About the Drive-On-Chip Design Example for Cyclone V Devices 2. Motor Control Boards 3. Drive-On-Chip Design Example for Cyclone V Devices Features 4. Getting Started 5. Building the Design 6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console 7. About the Scaling of Feedback Signals 8. Motor Control Software 9. Functional Description of the Drive-On-Chip Design Example 10. Achieving Timing Closure on a Motor Control Design 11. Design Security Recommendations 12. Reference Documents for the Drive-on-Chip Design Example 13. Document Revision History for AN 669: Drive-on-Chip Reference Design
4. Getting Started x
4.1. Software Requirements for the Drive-On-Chip Design Example for Cyclone V Devices 4.2. Downloading and Installing the Drive-On-Chip Design Example for Cyclone V Devices 4.3. Setting Up the Motor Control Board with your Development Board 4.4. Programming the Hardware onto the Device 4.5. Setting Up Terminal Emulator 4.6. Downloading the HPS Software to the Device
4.6. Downloading the HPS Software to the Device x
4.6.1. Downloading the HPS Software with the Arm GUI 4.6.2. Downloading the HPS Software with the Arm Script
5. Building the Design x
5.1. Compiling the Drive-on-Chip Design Example 5.2. Preparing the µC/OS-II HPS Software Files 5.3. Compiling the µC/OS-II HPS Software 5.4. Creating and Booting an HPS SD Card Software Image 5.5. Creating and Booting a SD Card with both Software Image and Hardware Image
5.3. Compiling the µC/OS-II HPS Software x
5.3.1. Compiling the µC/OS-II HPS Software with the Arm GUI 5.3.2. Compiling the µC/OS-II HPS Software with the Arm Script
6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console x
6.1. System Console GUI Upper Pane for the Drive-On-Chip Design Example 6.2. System Console GUI Lower Pane for the Drive-On-Chip Design Example 6.3. Vibration Suppression Tab 6.4. Controlling the DC-DC Converter 6.5. Tuning the PI Controller Gains 6.6. Controlling the Speed and Position Demonstrations 6.7. Monitoring Performance
6.3. Vibration Suppression Tab x
6.3.1. About the Demonstration 6.3.2. Starting the Demonstration 6.3.3. FFT0 and FFT1 Graphs 6.3.4. Setting Up FFT 6.3.5. Setting Up Command Waveform 6.3.6. Setting Up Second Order IIR Filter
7. About the Scaling of Feedback Signals x
7.1. Signal Sensing in Sigma-Delta ADCs 7.2. Signal Scaling in the Software of the Drive-On-Chip Design Example 7.3. Scale Factors for the Drive-On-Chip Design Example in the System Console Toolkit
8. Motor Control Software x
8.1. Viewing Motor Control Software Help Files 8.2. Software Application Configuration Files 8.3. Defining a New Motor or Encoder Type 8.4. SoC HPS Motor Control Software Project 8.5. Building the HPS Preloader
9. Functional Description of the Drive-On-Chip Design Example x
9.1. Processor Subsystem 9.2. Six-channel PWM Interface 9.3. DC Link Monitor 9.4. Drive System Monitor 9.5. Quadrature Encoder Interface 9.6. Sigma-Delta ADC Interface for Drive Axes 9.7. DC-DC Converter 9.8. Motor Control Modes 9.9. FOC Subsystem 9.10. FFTs 9.11. DEKF Technique for Battery Management 9.12. Signals 9.13. Registers
9.4. Drive System Monitor x
9.4.1. Drive System Monitor States for the Drive-On-Chip Design Example
9.6. Sigma-Delta ADC Interface for Drive Axes x
9.6.1. Offset Adjustment for Sigma-Delta ADC Interface
9.7. DC-DC Converter x
9.7.1. DC-DC Control Simulink Models 9.7.2. Sigma-Delta ADC Interface for DC-DC Converter
9.7.1. DC-DC Control Simulink Models x
9.7.1.1. DC-DC Control Block 9.7.1.2. Generating VHDL for the DSP Builder for Intel FPGAs Models for the DC-DC Converter
9.7.1.1. DC-DC Control Block x
9.7.1.1.1. DC-DC Model and VHDL Entity Signal Names and Data Format
9.9. FOC Subsystem x
9.9.1. DSP Builder for Intel FPGAs Model for the Drive-On-Chip Designs 9.9.2. Avalon Memory-Mapped Interface 9.9.3. About DSP Builder for Intel FPGAs 9.9.4. DSP Builder for Intel FPGAs Folding 9.9.5. DSP Builder for Intel FPGAs Model Resource Usage 9.9.6. DSP Builder for Intel FPGAs Design Guidelines 9.9.7. Generating VHDL for the DSP Builder Models for the Drive-On-Chip Reference Designs
9.10. FFTs x
9.10.1. Servo FFTs 9.10.2. Vibration Suppression 9.10.3. Command Waveform 9.10.4. IIR Filter 9.10.5. IIR Filter Tuning Parameters 9.10.6. IIR Filter Examples 9.10.7. Vibration Detection
9.10.1. Servo FFTs x
9.10.1.1. Running test_servofft.mdl
10. Achieving Timing Closure on a Motor Control Design x
10.1. Optimizing Motor Control Designs
1. About the Drive-On-Chip Design Example for Cyclone V Devices
2. Motor Control Boards
3. Drive-On-Chip Design Example for Cyclone V Devices Features
4. Getting Started
5. Building the Design
6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console
7. About the Scaling of Feedback Signals
8. Motor Control Software
9. Functional Description of the Drive-On-Chip Design Example
10. Achieving Timing Closure on a Motor Control Design
11. Design Security Recommendations
12. Reference Documents for the Drive-on-Chip Design Example
13. Document Revision History for AN 669: Drive-on-Chip Reference Design

9.9.1. DSP Builder for Intel FPGAs Model for the Drive-On-Chip Designs

The top-level model is a simple dummy testbench with constant inputs of the correct arithmetic types to control hardware generation, which includes the FOC algorithm model.
Figure 46. DSP Builder for Intel FPGAs Model

The FOC algorithm comprises the FOC algorithm block and a latch block for implementing the integrators necessary for the PI controllers in the FOC algorithm. DSP Builder for Intel FPGAs implements the latches outside because of limitations of the folding synthesis.

The design includes fixed-point and floating-point models that implement the FOC algorithm.

Each model calls a corresponding .m setup script during initialization to set up the arithmetic precision, folding factor, and target clock speed. The folding factor is set to a large value to minimize resource usage.

Table 18.  Default settings in Setup Script
Model Folding Factor Clock Speed (MHz) Input Precision Output Precision
Fixed point 500 100 sfix16En10 sfix32En10
Floating point 500 100 sfix32En10 sfix32En10

The following models generate the FOC block including the Avalon memory-mapped interface:

  • DFf_float_alu_av.slx for floating-point designs
  • DFf_fixp16_alu_av.slx for fixed-point designs

A Simulink* library model contains the main FOC algorithm code, which the other models refer to:

  • foc_blocks.slx
Level Two Title