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1. About the Drive-On-Chip Design Example for Cyclone V Devices
2. Motor Control Boards
3. Drive-On-Chip Design Example for Cyclone V Devices Features
4. Getting Started
5. Building the Design
6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console
7. About the Scaling of Feedback Signals
8. Motor Control Software
9. Functional Description of the Drive-On-Chip Design Example
10. Achieving Timing Closure on a Motor Control Design
11. Design Security Recommendations
12. Reference Documents for the Drive-on-Chip Design Example
13. Document Revision History for AN 669: Drive-on-Chip Reference Design
4.1. Software Requirements for the Drive-On-Chip Design Example for Cyclone V Devices
4.2. Downloading and Installing the Drive-On-Chip Design Example for Cyclone V Devices
4.3. Setting Up the Motor Control Board with your Development Board
4.4. Programming the Hardware onto the Device
4.5. Setting Up Terminal Emulator
4.6. Downloading the HPS Software to the Device
6.1. System Console GUI Upper Pane for the Drive-On-Chip Design Example
6.2. System Console GUI Lower Pane for the Drive-On-Chip Design Example
6.3. Vibration Suppression Tab
6.4. Controlling the DC-DC Converter
6.5. Tuning the PI Controller Gains
6.6. Controlling the Speed and Position Demonstrations
6.7. Monitoring Performance
9.1. Processor Subsystem
9.2. Six-channel PWM Interface
9.3. DC Link Monitor
9.4. Drive System Monitor
9.5. Quadrature Encoder Interface
9.6. Sigma-Delta ADC Interface for Drive Axes
9.7. DC-DC Converter
9.8. Motor Control Modes
9.9. FOC Subsystem
9.10. FFTs
9.11. DEKF Technique for Battery Management
9.12. Signals
9.13. Registers
9.9.1. DSP Builder for Intel FPGAs Model for the Drive-On-Chip Designs
9.9.2. Avalon Memory-Mapped Interface
9.9.3. About DSP Builder for Intel FPGAs
9.9.4. DSP Builder for Intel FPGAs Folding
9.9.5. DSP Builder for Intel FPGAs Model Resource Usage
9.9.6. DSP Builder for Intel FPGAs Design Guidelines
9.9.7. Generating VHDL for the DSP Builder Models for the Drive-On-Chip Reference Designs
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6-Channel PWM
The 6-channel PWM provides an 8-kHz switching period, and a start pulse every 16 kHz shortly before the reversal point of the PWM counter. This pulse goes to the ADC to start capturing data and when the ADC finishes it sends an interrupt to the processor. The interrupt output from the first axis and drive0 (doc_adc_irq) is connected to the processor. You may leave the interrupt outputs from the other axes unconnected.
The PWM provides synchronization between multiple PWM instances. To implement this feature the reference design programs the PWMs identically: in Qsys one instance is the master PWM and connects the sync_out port to the other PWM sync_in port. For additional instances, continue chaining the sync_out port from the last instance to the next sync_in port. For example:
sync_out (PWM0) to sync_in (PWM1) and sync_out(PWM1) to sync_in(PWM2)
An internal counter defines the PWM period from 0 to PWMMAX and then back to 0. The design configures it for an 8-kHz rate, and the internal clock rate of the PWM is 50 MHz. To achieve an 8-kHz period with an internal clock rate of 50 MHz, set the carrier register value to 3,125. Therefore:
carrier = (50 MHz / 8 kHz) / 2 = 3,125
Figure 15. PWM Counter Value
The carrier_latch output indicates to the position encoder to take a position reading. It is high for one clock cycle when the counter is at zero and at PWMMAX.
The start output indicates to the phase current ADC interfaces to start sampling. It is offset from the carrier_latch position, so it occurs at a fixed position before it. The pwm_trigger_up sets the trigger value when the PWM counter is counting up; pwm_trigger_down sets the trigger value when counting down (Table 14).