Intel® Advanced Link Analyzer: User Guide

Download PDF
ID 683448
Date 4/19/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Intel® Advanced Link Analyzer Overview 2. Functional Description 3. Tutorial: PCI Express* 8GT 4. Document Revision History for Intel® Advanced Link Analyzer User Guide
1. Intel® Advanced Link Analyzer Overview x
1.1. System Requirements 1.2. Installation 1.3. Program and File Types 1.4. Accessing the User Guide
2. Functional Description x
2.1. Intel® Advanced Link Analyzer Control Module 2.2. Intel® Advanced Link Analyzer Data Viewer Module 2.3. Intel® Advanced Link Analyzer Channel Viewer Module 2.4. Intel® Advanced Link Analyzer Batch Simulation Controller 2.5. Intel® Advanced Link Analyzer Channel Designer
2.1. Intel® Advanced Link Analyzer Control Module x
2.1.1. Constructing Communication Links in the Link Designer Module 2.1.2. Link and Simulation Setting 2.1.3. Transmitter Setting 2.1.4. Receiver Setting 2.1.5. IBIS-AMI Wrapper 2.1.6. Channel Setting 2.1.7. Batch Channel Simulation Configuration 2.1.8. Crosstalk Aggressor Transmitter Setting 2.1.9. Repeater and Retimer Configurations 2.1.10. Noise Source Link Component 2.1.11. System Options 2.1.12. Project Management Functions 2.1.13. Archiving and Unarchiving Projects 2.1.14. Device Model Importer 2.1.15. Analysis Functions and Pre-Simulation and Pre-Analysis Checklists 2.1.16. COM Analysis
2.1.3. Transmitter Setting x
2.1.3.1. Jitter/Noise Component 2.1.3.2. Transmitter Options 2.1.3.3. Characterization Data Access 2.1.3.4. IBIS-AMI Transmitter Configuration 2.1.3.5. Pulse Fitting Analysis 2.1.3.6. SNDR Analysis 2.1.3.7. Jnu/Jrms/EOJ Analysis 2.1.3.8. Clock Path Custom Transmitter
2.1.4. Receiver Setting x
2.1.4.1. Jitter/Noise Setting 2.1.4.2. Characterization Data Access 2.1.4.3. Receiver Options 2.1.4.4. IBIS-AMI Receiver Configuration 2.1.4.5. Custom Receiver With Input Clock
2.1.9. Repeater and Retimer Configurations x
2.1.9.1. Repeater/Retimer RX Configuration 2.1.9.2. Repeater/Retimer TX Configuration
2.3. Intel® Advanced Link Analyzer Channel Viewer Module x
2.3.1. Channel Plot Panel 2.3.2. Channel List Panel 2.3.3. Plot Option Panel
2.3.3. Plot Option Panel x
2.3.3.1. S-parameter Mode Panel 2.3.3.2. Plot Configuration Panel 2.3.3.3. Options
3. Tutorial: PCI Express* 8GT x
3.1. Methodology 3.2. Setup and Initialization 3.3. Analysis
3.2. Setup and Initialization x
3.2.1. Setting Up the Control Module 3.2.2. Constructing the Channel 3.2.3. Completing the System
1. Intel® Advanced Link Analyzer Overview
2. Functional Description
3. Tutorial: PCI Express* 8GT
4. Document Revision History for Intel® Advanced Link Analyzer User Guide

2.1.4.1. Jitter/Noise Setting

Intel® Advanced Link Analyzer provides extensive jitter and noise modeling and configuration capabilities. The receiver intrinsic jitter and noise types are categorized in the following table. You can configure each jitter and noise type by clicking Receiver Jitter Options, which leads to the Receiver Jitter/Noise Configuration window.

Intel® Advanced Link Analyzer uses a flat jitter/noise structure that assumes no overlapping among the jitter and noise components. Avoid double counting when inputting or importing jitter/noise figures. In the following figure, DJ contains DCD, ISI, PJ, and BUJ. This implies that when you specify DCD and BUJ, the DJ should not be used or the DJ figure should not contain any DCD and BUJ components.

Table 14.  Receiver Intrinsic Jitter and Noise Types

Name

Description

Unit

Support in Intel® Advanced Link Analyzer

Comments

DJ

Deterministic Jitter

UI

Yes

You can generate the receiver DJ by using a uniform distribution, dual-Dirac, or truncated Gaussian method. You can select the DJ generation method in the Receiver Jitter/Noise Configuration Window. The default receiver DJ method is dual-Dirac.

BUJ

Bounded Uncorrelated Jitter

UI

Yes

Same as receiver’s Deterministic Jitter. The default method is Uniform distribution. You can select the BUJ generation method in the Receiver Jitter/Noise Configuration Window.

RJ

Random Jitter

UI-RMS or

ps-RMS

Yes

RJ is assumed to be Gaussian. You can specify the receiver RJ in eighth pico-second (ps-RMS) or unit-interval (UI-RMS).

DN

Deterministic Noise

mV

Yes

You can generate the receiver DN by using a uniform distribution, dual-Dirac, or truncated Gaussian method. You can select the DN generation method in the Receiver Jitter/Noise Configuration Window. The default DJ method is uniform.

BUN

Bound Uncorrelated Noise

mV

Yes

Same as receiver DN above. The default method is Truncated Gaussian method. You can select the BUN generation method in the Receiver Jitter/Noise Configuration Window.

RN

Random Noise

mV-RMS

Yes

RN is assumed to be Gaussian.

Jitter PDF

Jitter Probability Density Function (PDF)

Jitter amplitude, Probability (Jitter amplitude can be in absolute time or UI (unit interval) unit)

Yes

Jitter PDF defines the jitter probability density function. The input format is jitter amplitude in second and probability. The following is a jitter PDF example:

-5e-12 1e-10

-4e-12 3e-7

-3e-12 1e-4

-2e-12 1e-2

-1e-12 0.29

0 0.4

1e-12 0.29

2e-12 1e-2

3e-12 1e-4

4e-12 3e-7

5e-12 1e-10

Noise PDF

Noise Probability Density Function

Noise amplitude, Probability

Yes

Noise PDF defines the noise probability density function. The input format is Noise amplitude in volt and probability. The following is a noise PDF example:

-50e-3 1e-10

-40e-3 3e-7

-30e-3 1e-4

-20e-3 1e-2

-10e-3 0.29

0 0.4

10e-3 0.29

20e-3 1e-2

30e-3 1e-4

40e-3 3e-7

50e-3 1e-10

InpN

Input Referred Noise

 V2/GHz

Yes (Except IBIS-AMI model and IBIS-AMI wrapper model)

Receiver input referred noise is specified as one-sided noise spectral density in the unit of V2/GHz. It produces receiver-setting dependent noise figure for link margin calculation.

Figure 48.  Intel® Advanced Link Analyzer Receiver Jitter/Noise Configuration Window

Clock path receiver uses the same jitter/noise configuration method as the data path receiver.

Figure 49. Specifying Clock Path Receiver Jitter/Noise
Level Two Title