Intel® Advanced Link Analyzer: User Guide

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ID 683448
Date 4/19/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® Advanced Link Analyzer Overview 2. Functional Description 3. Tutorial: PCI Express* 8GT 4. Document Revision History for Intel® Advanced Link Analyzer User Guide
1. Intel® Advanced Link Analyzer Overview x
1.1. System Requirements 1.2. Installation 1.3. Program and File Types 1.4. Accessing the User Guide
2. Functional Description x
2.1. Intel® Advanced Link Analyzer Control Module 2.2. Intel® Advanced Link Analyzer Data Viewer Module 2.3. Intel® Advanced Link Analyzer Channel Viewer Module 2.4. Intel® Advanced Link Analyzer Batch Simulation Controller 2.5. Intel® Advanced Link Analyzer Channel Designer
2.1. Intel® Advanced Link Analyzer Control Module x
2.1.1. Constructing Communication Links in the Link Designer Module 2.1.2. Link and Simulation Setting 2.1.3. Transmitter Setting 2.1.4. Receiver Setting 2.1.5. IBIS-AMI Wrapper 2.1.6. Channel Setting 2.1.7. Batch Channel Simulation Configuration 2.1.8. Crosstalk Aggressor Transmitter Setting 2.1.9. Repeater and Retimer Configurations 2.1.10. Noise Source Link Component 2.1.11. System Options 2.1.12. Project Management Functions 2.1.13. Archiving and Unarchiving Projects 2.1.14. Device Model Importer 2.1.15. Analysis Functions and Pre-Simulation and Pre-Analysis Checklists 2.1.16. COM Analysis
2.1.3. Transmitter Setting x
2.1.3.1. Jitter/Noise Component 2.1.3.2. Transmitter Options 2.1.3.3. Characterization Data Access 2.1.3.4. IBIS-AMI Transmitter Configuration 2.1.3.5. Pulse Fitting Analysis 2.1.3.6. SNDR Analysis 2.1.3.7. Jnu/Jrms/EOJ Analysis 2.1.3.8. Clock Path Custom Transmitter
2.1.4. Receiver Setting x
2.1.4.1. Jitter/Noise Setting 2.1.4.2. Characterization Data Access 2.1.4.3. Receiver Options 2.1.4.4. IBIS-AMI Receiver Configuration 2.1.4.5. Custom Receiver With Input Clock
2.1.9. Repeater and Retimer Configurations x
2.1.9.1. Repeater/Retimer RX Configuration 2.1.9.2. Repeater/Retimer TX Configuration
2.3. Intel® Advanced Link Analyzer Channel Viewer Module x
2.3.1. Channel Plot Panel 2.3.2. Channel List Panel 2.3.3. Plot Option Panel
2.3.3. Plot Option Panel x
2.3.3.1. S-parameter Mode Panel 2.3.3.2. Plot Configuration Panel 2.3.3.3. Options
3. Tutorial: PCI Express* 8GT x
3.1. Methodology 3.2. Setup and Initialization 3.3. Analysis
3.2. Setup and Initialization x
3.2.1. Setting Up the Control Module 3.2.2. Constructing the Channel 3.2.3. Completing the System
1. Intel® Advanced Link Analyzer Overview
2. Functional Description
3. Tutorial: PCI Express* 8GT
4. Document Revision History for Intel® Advanced Link Analyzer User Guide

2.1.4.2. Characterization Data Access

You can retrieve the receiver jitter values from the built-in device characterization database. Intel® Advanced Link Analyzer supports Intel® Arria® 10 GX/SX/GT, Stratix® V GT, Stratix® V GX and Arria® V GZ characterization database access upon request. For devices supported by IBIS-AMI Wrapper Technology, jitter/noise models are provided by the IBIS-AMI models, and the wrapper determines the correct jitter/noise values associated with the link settings. If you need this capability, contact My Intel support.

Use the following guidelines for characterization data access:

  • When Stratix® V GX, Stratix® V GT, Arria® V GZ or Intel® Arria® 10 GX/SX/GT is selected, the Characterization Data Access button appears and you can include the receiver jitter parameters in the simulation.
  • Characterization Data Access covers PVT variations. You can select the appropriate process, voltage, and temperature conditions that best match the desired operation conditions.
  • After clicking Characterization Data Access, Intel® Advanced Link Analyzer is configured to use the characterization data by:
    • Setting Jitter/Noise Component Mode for characterization data entries
    • Turning on the Jitter/Noise Data Lock
    • Importing device characterization data based on the jitter unit selection
      • RJ—Unit selection can be UI (RMS) or ps (RMS)
      • Other Jitter—Unit selection can be UI (pk-pk), UI (pk), ps (pk-pk), or ps (pk)

The Intel® Advanced Link Analyzer simulation engine uses this characterization data from the database.

Note:
  • Intel® Stratix® 10 receiver's jitter and noise values are sourced from the IBIS-AMI models or from user inputs per the IBIS-AMI model's documents.
  • The characterization data is displayed in the text box for reference purposes. The Intel® Advanced Link Analyzer simulation engine uses proprietary algorithms to accurately model the jitter and noise in the simulations.
  • You can unlock the jitter and noise contents by turning off the Jitter/Noise Data Lock. However, the jitter and noise models and values can be different from those when the Jitter/Noise Data Lock is turned on.
  • Characterization Data Access is supported when the data rate is in the following range:
    • Stratix® V GX: 5 Gbps to 14.1 Gbps
    • Stratix® V GT: 19.6 Gbps to 28.1 Gbps
    • Arria® V GZ: 5 Gbps to 14.1 Gbps
    • Intel® Arria® 10 GX/SX: 3 Gbps to 17.4 Gbps
    • Intel® Arria® 10 GT: 3 Gbps to maximum data rate specified in the data sheet
    When the data rate is out of the specified range, Intel® Advanced Link Analyzer displays a warning message, and no jitter data is retrieved. If you change the data rate, you must retrieve the new jitter data by clicking Characterization Data Access.
  • After changing the link and device configurations, such as data rate, bandwidth, and PVT condition, you must update the jitter value by clicking Characterization Data Access.
  • When the Jitter/Noise Data Lock is turned on, Intel® Advanced Link Analyzer examines whether the jitter data matches the simulation configuration during the following conditions:
    • Start simulation
    • Save link configuration
    • In batch simulation mode, jitter data is retrieved and calculated based on the link configuration

    When the link configuration exceeds the supporting range of Characterization Data Access, a warning message (conditions 1 and 2) is shown and jitter is reset (all conditions).

Figure 50. Characterization Data Access: PVT Conditions and Jitter/Noise Lock
Characterization Data Access: PVT Conditions and Jitter/Noise Lock
Figure 51. Characterization Data Access Usage and Message

A message box appears when the Characterization Data Access button is clicked.

Figure 52.  Intel Receiver Jitter Data Usage Message Window
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