Intel® Advanced Link Analyzer: User Guide

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ID 683448
Date 4/19/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® Advanced Link Analyzer Overview 2. Functional Description 3. Tutorial: PCI Express* 8GT 4. Document Revision History for Intel® Advanced Link Analyzer User Guide
1. Intel® Advanced Link Analyzer Overview x
1.1. System Requirements 1.2. Installation 1.3. Program and File Types 1.4. Accessing the User Guide
2. Functional Description x
2.1. Intel® Advanced Link Analyzer Control Module 2.2. Intel® Advanced Link Analyzer Data Viewer Module 2.3. Intel® Advanced Link Analyzer Channel Viewer Module 2.4. Intel® Advanced Link Analyzer Batch Simulation Controller 2.5. Intel® Advanced Link Analyzer Channel Designer
2.1. Intel® Advanced Link Analyzer Control Module x
2.1.1. Constructing Communication Links in the Link Designer Module 2.1.2. Link and Simulation Setting 2.1.3. Transmitter Setting 2.1.4. Receiver Setting 2.1.5. IBIS-AMI Wrapper 2.1.6. Channel Setting 2.1.7. Batch Channel Simulation Configuration 2.1.8. Crosstalk Aggressor Transmitter Setting 2.1.9. Repeater and Retimer Configurations 2.1.10. Noise Source Link Component 2.1.11. System Options 2.1.12. Project Management Functions 2.1.13. Archiving and Unarchiving Projects 2.1.14. Device Model Importer 2.1.15. Analysis Functions and Pre-Simulation and Pre-Analysis Checklists 2.1.16. COM Analysis
2.1.3. Transmitter Setting x
2.1.3.1. Jitter/Noise Component 2.1.3.2. Transmitter Options 2.1.3.3. Characterization Data Access 2.1.3.4. IBIS-AMI Transmitter Configuration 2.1.3.5. Pulse Fitting Analysis 2.1.3.6. SNDR Analysis 2.1.3.7. Jnu/Jrms/EOJ Analysis 2.1.3.8. Clock Path Custom Transmitter
2.1.4. Receiver Setting x
2.1.4.1. Jitter/Noise Setting 2.1.4.2. Characterization Data Access 2.1.4.3. Receiver Options 2.1.4.4. IBIS-AMI Receiver Configuration 2.1.4.5. Custom Receiver With Input Clock
2.1.9. Repeater and Retimer Configurations x
2.1.9.1. Repeater/Retimer RX Configuration 2.1.9.2. Repeater/Retimer TX Configuration
2.3. Intel® Advanced Link Analyzer Channel Viewer Module x
2.3.1. Channel Plot Panel 2.3.2. Channel List Panel 2.3.3. Plot Option Panel
2.3.3. Plot Option Panel x
2.3.3.1. S-parameter Mode Panel 2.3.3.2. Plot Configuration Panel 2.3.3.3. Options
3. Tutorial: PCI Express* 8GT x
3.1. Methodology 3.2. Setup and Initialization 3.3. Analysis
3.2. Setup and Initialization x
3.2.1. Setting Up the Control Module 3.2.2. Constructing the Channel 3.2.3. Completing the System
1. Intel® Advanced Link Analyzer Overview
2. Functional Description
3. Tutorial: PCI Express* 8GT
4. Document Revision History for Intel® Advanced Link Analyzer User Guide

2.1.1. Constructing Communication Links in the Link Designer Module

The Link Designer module allows you to construct communication links.

Figure 2.  Intel® Advanced Link Analyzer Link Designer Module
Table 3.  Supported Transmitter, Channel, and Receiver Components

Transmitter (TX) Component

Channel/Link Component

Receiver (RX) Component

Intel Agilex®

  • Intel Agilex® 7 E-tile (wrapper support)
  • Intel Agilex® 7 P-tile (wrapper support)
  • Intel Agilex® 7 R-tile (wrapper support)
  • Intel Agilex® 7 F-tile FGT (wrapper support)
  • Intel Agilex® 7 F-tile FHT (wrapper support)

Channel

  • Transmission
  • Connector
  • Package

Intel Agilex®

  • Intel Agilex® 7 E-tile (wrapper support)
  • Intel Agilex® 7 P-tile (wrapper support)
  • Intel Agilex® 7 R-tile (wrapper support)
  • Intel Agilex® 7 F-tile FGT (wrapper support)
  • Intel Agilex® 7 F-tile FHT (wrapper support)

Stratix®

  • Stratix® V GX
  • Stratix® V GT
  • Intel® Stratix® 10 L-tile
  • Intel® Stratix® 10 H-tile
  • Intel® Stratix® 10 E-tile (wrapper support)
  • Intel® Stratix® 10 P-tile (wrapper support)

Crosstalk

  • Far-end Crosstalk
  • Near-end Crosstalk
  • Far-end Crosstalk w/ Aggressor
  • Near-end Crosstalk w/ Aggressor
  • Aggressor Transmission w/ Aggressor

Stratix®

  • Stratix® V GX
  • Stratix® V GT
  • Intel® Stratix® 10 L-tile (wrapper support)
  • Intel® Stratix® 10 H-tile (wrapper support)
  • Intel® Stratix® 10 E-tile (wrapper support)
  • Intel® Stratix® 10 P-tile (wrapper support)

Arria®

  • Arria® V GZ
  • Intel® Arria® 10 GX/SX
  • Intel® Arria® 10 GT

Channel Designer

  • Stripline
  • Microstrip
  • Coax RLGC
  • Ideal Transmission Line
  • PCB Via
  • Coupled Stripline
  • Coupled Microstrip
  • Channel Designer Module
  • PCB Stackup

Arria®

  • Arria® V GZ
  • Intel® Arria® 10 GX/SX
  • Intel® Arria® 10 GT

Generic

  • Custom
  • Clock Path Custom
  • PCI Express* 8GT
  • PCI Express* 16GT
  • PCI Express* 32GT

Basic Component

  • AC Coupling Capacitor
  • Shunt Capacitor
  • Series Inductor

Generic

  • Custom
  • Custom with Input Clock
  • PCI Express* 8GT
  • PCI Express* 16GT
  • PCI Express* 32GT

IBIS-AMI

  • IBIS-AMI
  • Clock IBIS-AMI

Clock Path Component

  • Clock Path Transmission
  • Clock Path TX Package
  • Clock Path RX Package

IBIS-AMI

  • IBIS-AMI
  • IBIS-AMI with Input Clock
Intel® Cyclone® 10
  • Intel® Cyclone® 10 GX
Link Component
  • Repeater/Retimer TX
  • Repeater/Retimer RX
  • Noise Source w/ Channel
Intel® Cyclone® 10
  • Intel® Cyclone® 10 GX

Intel® Advanced Link Analyzer supports the following simulations:

  • Intel TX to Intel RX
  • Intel TX to non-Intel RX
  • Non-Intel TX to Intel RX
Note:
  • Non-Intel to non-Intel link simulations are not supported.
  • For Intel® devices not listed in Supported Transmitter, Channel, and Receiver Components, contact My Intel® support and acquire the IBIS-AMI models.
  • You can add, remove, or update devices supported with wrapper technology to Intel® Advanced Link Analyzer after installing the tool. Refer to IBIS-AMI Wrapper for further details.

A link consists of a transmitter, a receiver, and one or more channel/link components. Select the transmitter, receiver, and channel/link components from the menus at the top of the Link Designer workspace.

After placing the link components in the workspace, click Connect to connect the components. In the connect mode, one or two connectors are shown on each component. Connect the link components by dragging the line from one connector to another. The Link Designer provides two types of connections—Right Angled Line and Straight Line. Right Angled Line is the default connection method. You can manually place test points into the link by clicking Test Point and connecting to the desired location in the link.

The following rules of link construction apply to the Link Designer module:

  • A transmitter can only have one output port or connector.
  • A receiver can only have one input port or connector.
  • A channel/link component has one input and one output port.
  • A test point can only be connected to an input port.
  • A connection between two components can be established from an output port to an input port.
  • A transmitter cannot be connected directly to a receiver.
  • A clock path channel component can only connect to another clock path component and be terminated by a clock path transmitter or receiver.

A link establishment checking algorithm constantly runs in the background, checking whether a link is established for simulations. When a link is established between a transmitter and receiver, the link lines become bold and color-coded. Bold black lines indicate signal paths, green lines indicate crosstalk signal paths, brown lines indicate clock signal paths, and purple lines point to test point port locations. The following figure shows an example link topology. A table of link components is displayed in the Channel tab for reference.

Figure 3.  Intel® Advanced Link Analyzer Link Designer with Channel Table

When a channel component (for example, a transmission line, connector, far-end crosstalk (FEXT), near-end crosstalk (NEXT), package, AC coupling capacitor, or shunt capacitor) is chosen, the Channel Wizard helps you verify or set the channel configuration.

Figure 4.  Intel® Advanced Link Analyzer Channel Wizard

The Channel Wizard displays the channel characteristics and allows you to verify the correctness of the channel component, such as a component represented by an S-parameter. The Channel Wizard allows you to select the following components:

  • channel type
  • port configuration
  • signal lanes (for multiple-lane S-parameters with eight and more ports)
  • crosstalk aggressor location (for multiple-lane S-parameters)
  • aggressor
  • series inductance value (in nH)
  • AC coupling capacitor value (in nF)
  • shunt capacitance value (in pF)

The Channel Wizard checks the integrity of the channel component in terms of passivity and causality characteristics. When the Channel Wizard detects passivity and causality violations, it displays messages about the severity of the violations in the text box on the left of the OK button. The levels of channel integrity violation are listed in the following tables. Intel® Advanced Link Analyzer provides the option to enforce or improve causality of the selected channel during a simulation when Enforce Causality is turned on.

Note: Channel integrity checking can be disabled or bypassed by setting Channel Integrity Check in the System Options window. Intel® has found that Intel® Advanced Link Analyzer's Channel Integrity Checking algorithm is compatible and reliable for a majority of channels. However, there are some exceptions, such as a S-parameter with an extensive amount of measurement noise across frequencies, that can lead to computation convergence issues. If this is the case, please disable Channel Integrity Checking.
Table 4.  Channel Passivity Check Results and Recommendations
Passivity Violation Check Results Impact on Link Simulation Accuracy Recommendations
No Passivity Violation No impact No action needed
Slight Passivity Violation There may not be a noticeable effect in the simulation result. The channel model can be further improved, but the improvement in terms of simulation results accuracy can be small.
Minor Passivity Violation There may be a noticeable effect in the simulation result. The channel model can be further improved. Simulation result accuracy can be reduced.
Passivity Violation Simulation result impact The channel model needs to be regenerated (by design tools) or re-taken (by instruments). The confidence of simulation results using this channel model is low.
Table 5.  Channel Causality Check Results and Recommendations
Causality Violation Check Results Impact on Link Simulation Accuracy Recommendations
Channel is causal No impact No action needed
Slight non-causal There may not be a noticeable effect in the simulation result The channel model can be further improved, but the improvement in terms of simulation results accuracy can be small.
Somewhat non-causal There may be a noticeable effect in the simulation result The channel model can be further improved. Simulation result accuracy can be reduced.
Non-causal Simulation result impact The channel model needs to be regenerated (by design tools) or re-taken (by instruments). The confidence of simulation results using this channel model is low.
To select another S-parameter within the Channel Wizard, click Change Channel.
Note: Intel recommends replacing or changing a channel with one of the same channel types. Link Designer allows channel changing with different channel types, but you might see inconsistent channel icons in the design workspace.

An existing channel can be changed by adding a new channel component or by modifying an existing channel component. Right-click in the Link designer module and select Properties.

When using the package channel component, follow these guidelines:

  • Package models should be placed next to the devices.
  • Each device can have only one package model. Therefore, the external package model can only be used when the device’s package type is “Custom.”
  • The simulation engine uses the package model type to identify the boundary of the devices and generate a waveform for observation and analysis.
  • The package model is treated similar to the “Transmission” channel type. Therefore, use the “Transmission” channel type even if the model represents a physical package (in your system), but it is not a package of the TX and RX.
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