Arria® V Device Overview

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ID 683440
Date 11/20/2020
Public
Document Table of Contents
Document Table of Contents x
1. Arria V Device Overview
1. Arria V Device Overview x
1.1. Key Advantages of Arria® V Devices 1.2. Summary of Arria® V Features 1.3. Arria® V Device Variants and Packages 1.4. I/O Vertical Migration for Arria® V Devices 1.5. Adaptive Logic Module 1.6. Variable-Precision DSP Block 1.7. Embedded Memory Blocks 1.8. Clock Networks and PLL Clock Sources 1.9. FPGA General Purpose I/O 1.10. PCIe* Gen1, Gen2, and Gen 3 Hard IP 1.11. External Memory Interface 1.12. Low-Power Serial Transceivers 1.13. SoC with HPS 1.14. Dynamic Reconfiguration 1.15. Enhanced Configuration and Configuration via Protocol 1.16. Power Management 1.17. Document Revision History
1.3. Arria® V Device Variants and Packages x
1.3.1. Arria V GX 1.3.2. Arria V GT 1.3.3. Arria V GZ 1.3.4. Arria V SX 1.3.5. Arria V ST
1.3.1. Arria V GX x
1.3.1.1. Available Options 1.3.1.2. Maximum Resources 1.3.1.3. Package Plan
1.3.2. Arria V GT x
1.3.2.1. Available Options 1.3.2.2. Maximum Resources 1.3.2.3. Package Plan
1.3.3. Arria V GZ x
1.3.3.1. Available Options 1.3.3.2. Maximum Resources 1.3.3.3. Package Plan
1.3.4. Arria V SX x
1.3.4.1. Available Options 1.3.4.2. Maximum Resources 1.3.4.3. Package Plan
1.3.5. Arria V ST x
1.3.5.1. Available Options 1.3.5.2. Maximum Resources 1.3.5.3. Package Plan
1.7. Embedded Memory Blocks x
1.7.1. Types of Embedded Memory 1.7.2. Embedded Memory Capacity in Arria V Devices 1.7.3. Embedded Memory Configurations
1.11. External Memory Interface x
1.11.1. Hard and Soft Memory Controllers 1.11.2. External Memory Performance 1.11.3. HPS External Memory Performance
1.12. Low-Power Serial Transceivers x
1.12.1. Transceiver Channels 1.12.2. PMA Features 1.12.3. PCS Features
1.13. SoC with HPS x
1.13.1. HPS Features 1.13.2. FPGA Configuration and Processor Booting 1.13.3. Hardware and Software Development
1.13.1. HPS Features x
1.13.1.1. System Peripherals and Debug Access Port 1.13.1.2. HPS–FPGA AXI Bridges 1.13.1.3. HPS SDRAM Controller Subsystem
1.14. Dynamic Reconfiguration x
1.14.1. Dynamic Reconfiguration
1. Arria V Device Overview

1.6. Variable-Precision DSP Block

Arria® V devices feature a variable-precision DSP block that supports these features:

  • Configurable to support signal processing precisions ranging from 9 x 9, 18 x 18, 27 x 27, and 36 x 36 bits natively
  • A 64-bit accumulator
  • Double accumulator
  • A hard preadder that is available in both 18- and 27-bit modes
  • Cascaded output adders for efficient systolic finite impulse response (FIR) filters
  • Dynamic coefficients
  • 18-bit internal coefficient register banks
  • Enhanced independent multiplier operation
  • Efficient support for single-precision floating point arithmetic
  • The inferability of all modes by the Intel® Quartus® Prime design software
Table 14.  Variable-Precision DSP Block Configurations for Arria® V Devices
Usage Example Multiplier Size (Bit) DSP Block Resource
Low precision fixed point for video applications Three 9 x 9 1
Medium precision fixed point in FIR filters Two 18 x 18 1
FIR filters Two 18 x 18 with accumulate 1
Single-precision floating-point implementations One 27 x 27 1
Very high precision fixed point implementations One 36 x 36 2

You can configure each DSP block during compilation as independent three 9 x 9, two 18 x 18, or one 27 x 27 multipliers. Using two DSP block resources, you can also configure a 36 x 36 multiplier for high-precision applications. With a dedicated 64 bit cascade bus, you can cascade multiple variable-precision DSP blocks to implement even higher precision DSP functions efficiently.

Table 15.  Number of Multipliers in Arria® V DevicesThe table lists the variable-precision DSP resources by bit precision for each Arria® V device.
Variant Member Code Variable-precision DSP Block Independent Input and Output Multiplications Operator 18 x 18 Multiplier Adder Mode 18 x 18 Multiplier Adder Summed with 36 bit Input
9 x 9 Multiplier 18 x 18 Multiplier 27 x 27 Multiplier 36 x 36 Multiplier
Arria V GX A1 240 720 480 240 — 240 240
A3 396 1,188 792 396 — 396 396
A5 600 1,800 1,200 600 — 600 600
A7 800 2,400 1,600 800 — 800 800
B1 920 2,760 1,840 920 — 920 920
B3 1,045 3,135 2,090 1,045 — 1,045 1,045
B5 1,092 3,276 2,184 1,092 — 1,092 1,092
B7 1,156 3,468 2,312 1,156 — 1,156 1,156
Arria V GT C3 396 1,188 792 396 — 396 396
C7 800 2,400 1,600 800 — 800 800
D3 1,045 3,135 2,090 1,045 — 1,045 1,045
D7 1,156 3,468 2,312 1,156 — 1,156 1,156
Arria V GZ E1 800 2,400 1,600 800 400 800 800
E3 1,044 3,132 2,088 1,044 522 1,044 1,044
E5 1,092 3,276 2,184 1,092 546 1,092 1,092
E7 1,139 3,417 2,278 1,139 569 1,139 1,139
Arria V SX B3 809 2,427 1,618 809 — 809 809
B5 1,090 3,270 2,180 1,090 — 1,090 1,090
Arria V ST D3 809 2,427 1,618 809 — 809 809
D5 1,090 3,270 2,180 1,090 — 1,090 1,090
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