Arria® V Device Overview

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ID 683440
Date 11/20/2020
Public
Document Table of Contents
Document Table of Contents x
1. Arria V Device Overview
1. Arria V Device Overview x
1.1. Key Advantages of Arria® V Devices 1.2. Summary of Arria® V Features 1.3. Arria® V Device Variants and Packages 1.4. I/O Vertical Migration for Arria® V Devices 1.5. Adaptive Logic Module 1.6. Variable-Precision DSP Block 1.7. Embedded Memory Blocks 1.8. Clock Networks and PLL Clock Sources 1.9. FPGA General Purpose I/O 1.10. PCIe* Gen1, Gen2, and Gen 3 Hard IP 1.11. External Memory Interface 1.12. Low-Power Serial Transceivers 1.13. SoC with HPS 1.14. Dynamic Reconfiguration 1.15. Enhanced Configuration and Configuration via Protocol 1.16. Power Management 1.17. Document Revision History
1.3. Arria® V Device Variants and Packages x
1.3.1. Arria V GX 1.3.2. Arria V GT 1.3.3. Arria V GZ 1.3.4. Arria V SX 1.3.5. Arria V ST
1.3.1. Arria V GX x
1.3.1.1. Available Options 1.3.1.2. Maximum Resources 1.3.1.3. Package Plan
1.3.2. Arria V GT x
1.3.2.1. Available Options 1.3.2.2. Maximum Resources 1.3.2.3. Package Plan
1.3.3. Arria V GZ x
1.3.3.1. Available Options 1.3.3.2. Maximum Resources 1.3.3.3. Package Plan
1.3.4. Arria V SX x
1.3.4.1. Available Options 1.3.4.2. Maximum Resources 1.3.4.3. Package Plan
1.3.5. Arria V ST x
1.3.5.1. Available Options 1.3.5.2. Maximum Resources 1.3.5.3. Package Plan
1.7. Embedded Memory Blocks x
1.7.1. Types of Embedded Memory 1.7.2. Embedded Memory Capacity in Arria V Devices 1.7.3. Embedded Memory Configurations
1.11. External Memory Interface x
1.11.1. Hard and Soft Memory Controllers 1.11.2. External Memory Performance 1.11.3. HPS External Memory Performance
1.12. Low-Power Serial Transceivers x
1.12.1. Transceiver Channels 1.12.2. PMA Features 1.12.3. PCS Features
1.13. SoC with HPS x
1.13.1. HPS Features 1.13.2. FPGA Configuration and Processor Booting 1.13.3. Hardware and Software Development
1.13.1. HPS Features x
1.13.1.1. System Peripherals and Debug Access Port 1.13.1.2. HPS–FPGA AXI Bridges 1.13.1.3. HPS SDRAM Controller Subsystem
1.14. Dynamic Reconfiguration x
1.14.1. Dynamic Reconfiguration
1. Arria V Device Overview

1.15. Enhanced Configuration and Configuration via Protocol

Table 23.  Configuration Schemes and Features of Arria® V Devices Arria® V devices support 1.8 V, 2.5 V, 3.0 V, and 3.3 V 19 programming voltages and several configuration schemes.
Mode Data Width Max Clock Rate (MHz) Max Data Rate (Mbps) Decompression Design Security Remote System Update
AS through the EPCS and EPCQ serial configuration device 1 bit, 4 bits 100 — Yes Yes Yes
PS through CPLD or external microcontroller 1 bit 125 125 Yes Yes —
FPP 8 bits 125 — Yes Yes Parallel flash loader
16 bits 125 — Yes Yes
32 bits20 100 — Yes Yes
CvP (PCIe) x1, x2, x4, and x8 lanes — — Yes Yes —
JTAG 1 bit 33 33 — — —
Configuration via HPS 16 bits 125 — Yes Yes Parallel flash loader
32 bits 100 — Yes Yes

Instead of using an external flash or ROM, you can configure the Arria® V devices through PCIe using CvP. The CvP mode offers the fastest configuration rate and flexibility with the easy-to-use PCIe hard IP block interface. The Arria® V CvP implementation conforms to the PCIe 100 ms power-up-to-active time requirement.

Note: Although Arria® V GZ devices support PCIe Gen3, you can use only PCIe Gen1 and PCIe Gen2 for CvP configuration scheme.
Related Information
19 Arria® V GZ does not support 3.3 V.
20 Arria® V GZ only
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