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1.1. Key Advantages of Arria® V Devices
1.2. Summary of Arria® V Features
1.3. Arria® V Device Variants and Packages
1.4. I/O Vertical Migration for Arria® V Devices
1.5. Adaptive Logic Module
1.6. Variable-Precision DSP Block
1.7. Embedded Memory Blocks
1.8. Clock Networks and PLL Clock Sources
1.9. FPGA General Purpose I/O
1.10. PCIe* Gen1, Gen2, and Gen 3 Hard IP
1.11. External Memory Interface
1.12. Low-Power Serial Transceivers
1.13. SoC with HPS
1.14. Dynamic Reconfiguration
1.15. Enhanced Configuration and Configuration via Protocol
1.16. Power Management
1.17. Document Revision History
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1.13.1. HPS Features
The HPS consists of a dual-core Arm* Cortex* -A9 MPCore* processor, a rich set of peripherals, and a shared multiport SDRAM memory controller, as shown in the following figure.
Figure 12. HPS with Dual-Core Arm* Cortex* -A9 MPCore* Processor