Arria® V Device Overview

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ID 683440
Date 11/20/2020
Public
Document Table of Contents
Document Table of Contents x
1. Arria V Device Overview
1. Arria V Device Overview x
1.1. Key Advantages of Arria® V Devices 1.2. Summary of Arria® V Features 1.3. Arria® V Device Variants and Packages 1.4. I/O Vertical Migration for Arria® V Devices 1.5. Adaptive Logic Module 1.6. Variable-Precision DSP Block 1.7. Embedded Memory Blocks 1.8. Clock Networks and PLL Clock Sources 1.9. FPGA General Purpose I/O 1.10. PCIe* Gen1, Gen2, and Gen 3 Hard IP 1.11. External Memory Interface 1.12. Low-Power Serial Transceivers 1.13. SoC with HPS 1.14. Dynamic Reconfiguration 1.15. Enhanced Configuration and Configuration via Protocol 1.16. Power Management 1.17. Document Revision History
1.3. Arria® V Device Variants and Packages x
1.3.1. Arria V GX 1.3.2. Arria V GT 1.3.3. Arria V GZ 1.3.4. Arria V SX 1.3.5. Arria V ST
1.3.1. Arria V GX x
1.3.1.1. Available Options 1.3.1.2. Maximum Resources 1.3.1.3. Package Plan
1.3.2. Arria V GT x
1.3.2.1. Available Options 1.3.2.2. Maximum Resources 1.3.2.3. Package Plan
1.3.3. Arria V GZ x
1.3.3.1. Available Options 1.3.3.2. Maximum Resources 1.3.3.3. Package Plan
1.3.4. Arria V SX x
1.3.4.1. Available Options 1.3.4.2. Maximum Resources 1.3.4.3. Package Plan
1.3.5. Arria V ST x
1.3.5.1. Available Options 1.3.5.2. Maximum Resources 1.3.5.3. Package Plan
1.7. Embedded Memory Blocks x
1.7.1. Types of Embedded Memory 1.7.2. Embedded Memory Capacity in Arria V Devices 1.7.3. Embedded Memory Configurations
1.11. External Memory Interface x
1.11.1. Hard and Soft Memory Controllers 1.11.2. External Memory Performance 1.11.3. HPS External Memory Performance
1.12. Low-Power Serial Transceivers x
1.12.1. Transceiver Channels 1.12.2. PMA Features 1.12.3. PCS Features
1.13. SoC with HPS x
1.13.1. HPS Features 1.13.2. FPGA Configuration and Processor Booting 1.13.3. Hardware and Software Development
1.13.1. HPS Features x
1.13.1.1. System Peripherals and Debug Access Port 1.13.1.2. HPS–FPGA AXI Bridges 1.13.1.3. HPS SDRAM Controller Subsystem
1.14. Dynamic Reconfiguration x
1.14.1. Dynamic Reconfiguration
1. Arria V Device Overview

1.12.3. PCS Features

The Arria® V core logic connects to the PCS through an 8, 10, 16, 20, 32, 40, 64, 66, or 67 bit interface, depending on the transceiver data rate and protocol. Arria® V devices contain PCS hard IP to support PCIe Gen1, Gen2, and Gen3, GbE, Serial RapidIO® (SRIO), GPON, and CPRI.

All other standard and proprietary protocols within the following speed ranges are also supported:

  • 611 Mbps to 6.5536 Gbps—supported through the custom double-width mode (up to 6.5536 Gbps) and custom single-width mode (up to 3.75 Gbps) of the transceiver PCS hard IP.
  • 6.5536 Gbps to 10.3125 Gbps—supported through dedicated 80 or 64 bit interface that bypass the PCS hard IP and connects the PMA directly to the core logic. In Arria® V GZ, this is supported in the transceiver PCS hard IP.
Table 21.  Transceiver PCS Features for Arria® V GX, GT, ST, and SX Devices
PCS Support13 Data Rates (Gbps) Transmitter Data Path Feature Receiver Data Path Feature
Custom single- and double-width modes 0.611 to ~6.5536
  • Phase compensation FIFO
  • Byte serializer
  • 8B/10B encoder
  • Word aligner
  • 8B/10B decoder
  • Byte deserializer
  • Phase compensation FIFO
SRIO 1.25 to 6.25
Serial ATA 1.5, 3.0, 6.0

PCIe Gen1

(x1, x2, x4, x8)

2.5 and 5.0
  • Phase compensation FIFO
  • Byte serializer
  • 8B/10B encoder
  • PIPE 2.0 interface to the core logic
  • Word aligner
  • 8B/10B decoder
  • Byte deserializer
  • Phase compensation FIFO
  • Rate match FIFO
  • PIPE 2.0 interface to the core logic

PCIe Gen2 14

(x1, x2, x4)

GbE 1.25
  • Phase compensation FIFO
  • Byte serializer
  • 8B/10B encoder
  • Word aligner
  • 8B/10B decoder
  • Byte deserializer
  • Phase compensation FIFO
  • Rate match FIFO
XAUI15 3.125
  • Phase compensation FIFO
  • Byte serializer
  • 8B/10B encoder
  • XAUI state machine for bonding four channels
  • Word aligner
  • 8B/10B decoder
  • Byte deserializer
  • Phase compensation FIFO
  • XAUI state machine for realigning four channels
  • Deskew FIFO circuitry
SDI 0.2716, 1.485, 2.97
  • Phase compensation FIFO
  • Byte serializer
  • Byte deserializer
  • Phase compensation FIFO
GPON17 1.25 and 2.5
CPRI18 0.6144 to 6.144
  • Phase compensation FIFO
  • Byte serializer
  • 8B/10B encoder
  • TX deterministic latency
  • Word aligner
  • 8B/10B decoder
  • Byte deserializer
  • Phase compensation FIFO
  • RX deterministic latency
Table 22.  Transceiver PCS Features for Arria® V GZ Devices
Protocol Data Rates (Gbps) Transmitter Data Path Features Receiver Data Path Features
Custom PHY 0.6 to 9.80
  • Phase compensation FIFO
  • Byte serializer
  • 8B/10B encoder
  • Bit-slip
  • Channel bonding
  • Word aligner
  • Deskew FIFO
  • Rate match FIFO
  • 8B/10B decoder
  • Byte deserializer
  • Byte ordering
GPON 1.25 and 2.5
Custom 10G PHY 9.98 to 12.5
  • TX FIFO
  • Gear box
  • Bit-slip
  • RX FIFO
  • Gear box

PCIe Gen1

(x1, x2 x4, x8)

2.5 and 5.0
  • Phase compensation FIFO
  • Byte serializer
  • 8B/10B encoder
  • Bit-slip
  • Channel bonding
  • PIPE 2.0 interface to core logic
  • Word aligner
  • Deskew FIFO
  • Rate match FIFO
  • 8B/10B decoder
  • Byte deserializer,
  • Byte ordering
  • PIPE 2.0 interface to core logic

PCIe Gen2

(x1, x2, x4, x8)

PCIe Gen3

(x1, x2, x4, x8)

8.0
  • Phase compensation FIFO
  • 128B/130B encoder
  • Scrambler
  • Gear box
  • Bit-slip
  • Block synchronization
  • Rate match FIFO
  • 128B/130B decoder
  • Descrambler
  • Phase compensation FIFO
10GbE 10.3125
  • TX FIFO
  • 64B/66B encoder
  • Scrambler
  • Gear box
  • RX FIFO
  • 64B/66B decoder
  • Descrambler
  • Block synchronization
  • Gear box
Interlaken 3.125 to 12.5
  • TX FIFO
  • Frame generator
  • CRC-32 generator
  • Scrambler
  • Disparity generator
  • Gear box
  • RX FIFO
  • Frame generator
  • CRC-32 checker
  • Frame decoder
  • Descrambler
  • Disparity checker
  • Block synchronization
  • Gear box
40GBASE-R Ethernet 4 x 10.3125
  • TX FIFO
  • 64B/66B encoder
  • Scrambler
  • Alignment marker insertion
  • Gearbox
  • Block stripper
  • RX FIFO
  • 64B/66B decoder
  • Descrambler
  • Lane reorder
  • Deskew
  • Alignment marker lock
  • Block synchronization
  • Gear box
  • Destripper
100GBASE-R Ethernet 10 x 10.3125
40G and 100G OTN (4 +1) x 11.3
  • TX FIFO
  • Channel bonding
  • Byte serializer
  • RX FIFO
  • Lane deskew
  • Byte deserializer
(10 +1) x 11.3
GbE 1.25
  • Phase compensation FIFO
  • Byte serializer
  • 8B/10B encoder
  • Bit-slip
  • Channel bonding
  • GbE state machine
  • Word aligner
  • Deskew FIFO
  • Rate match FIFO
  • 8B/10B decoder
  • Byte deserializer
  • Byte ordering
  • GbE state machine
XAUI 3.125 to 4.25
  • Phase compensation FIFO
  • Byte serializer
  • 8B/10B encoder
  • Bit-slip
  • Channel bonding
  • XAUI state machine for bonding four channels
  • Word aligner
  • Deskew FIFO
  • Rate match FIFO
  • 8B/10B decoder
  • Byte deserializer
  • Byte ordering
  • XAUI state machine for realigning four channels
SRIO 1.25 to 6.25
  • Phase compensation FIFO
  • Byte serializer
  • 8B/10B encoder
  • Bit-slip
  • Channel bonding
  • SRIO V2.1-compliant x2 and x4 channel bonding
  • Word aligner
  • Deskew FIFO
  • Rate match FIFO
  • 8B/10B decoder
  • Byte deserializer
  • Byte ordering
  • SRIO V2.1-compliant x2 and x4 deskew state machine
13 Data rates above 6.5536 Gbps up to 10.3125 Gbps, such as 10GBASE-R, are supported through the soft PCS.
14 PCIe Gen2 is supported only through the PCIe hard IP.
15 XAUI is supported through the soft PCS.
16 The 0.27 Gbps data rate is supported using oversampling user logic that you must implement in the FPGA fabric.
17 The GPON standard does not support burst mode.
18 CPRI data rates above 6.5536 Gbps, such as 9.8304 Gbps, are supported through the soft PCS.
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