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1.1. Key Advantages of Arria® V Devices
1.2. Summary of Arria® V Features
1.3. Arria® V Device Variants and Packages
1.4. I/O Vertical Migration for Arria® V Devices
1.5. Adaptive Logic Module
1.6. Variable-Precision DSP Block
1.7. Embedded Memory Blocks
1.8. Clock Networks and PLL Clock Sources
1.9. FPGA General Purpose I/O
1.10. PCIe* Gen1, Gen2, and Gen 3 Hard IP
1.11. External Memory Interface
1.12. Low-Power Serial Transceivers
1.13. SoC with HPS
1.14. Dynamic Reconfiguration
1.15. Enhanced Configuration and Configuration via Protocol
1.16. Power Management
1.17. Document Revision History
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1.11.3. HPS External Memory Performance
Interface | Voltage (V) | HPS Hard Controller (MHz) |
---|---|---|
DDR3 SDRAM | 1.5 | 533 |
1.35 | 533 | |
LPDDR2 SDRAM | 1.2 | 333 |
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