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1.1. Key Advantages of Arria® V Devices
1.2. Summary of Arria® V Features
1.3. Arria® V Device Variants and Packages
1.4. I/O Vertical Migration for Arria® V Devices
1.5. Adaptive Logic Module
1.6. Variable-Precision DSP Block
1.7. Embedded Memory Blocks
1.8. Clock Networks and PLL Clock Sources
1.9. FPGA General Purpose I/O
1.10. PCIe* Gen1, Gen2, and Gen 3 Hard IP
1.11. External Memory Interface
1.12. Low-Power Serial Transceivers
1.13. SoC with HPS
1.14. Dynamic Reconfiguration
1.15. Enhanced Configuration and Configuration via Protocol
1.16. Power Management
1.17. Document Revision History
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1.12.2. PMA Features
To prevent core and I/O noise from coupling into the transceivers, the PMA block is isolated from the rest of the chip—ensuring optimal signal integrity. For the transceivers, you can use the channel PLL of an unused receiver PMA as an additional transmit PLL.
Features | Capability |
---|---|
Backplane support |
|
Chip-to-chip support |
|
PLL-based clock recovery | Superior jitter tolerance |
Programmable serializer and deserializer (SERDES) | Flexible SERDES width |
Equalization and pre-emphasis |
|
Ring oscillator transmit PLLs | 611 Mbps to 10.3125 Gbps |
LC oscillator ATX transmit PLLs (Arria V GZ devices only) |
600 Mbps to 12.5 Gbps |
Input reference clock range | 27 MHz to 710 MHz |
Transceiver dynamic reconfiguration | Allows the reconfiguration of a single channel without affecting the operation of other channels |