Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

6.4.40. signal_error_exceed_max_pending_reads

Prototype:

signal_error_exceed_max_pending_reads

Arguments:

Verilog HDL: None

VHDL: N.A.

Returns:

void

Description:

Notifies the testbench of the error condition, in which the slave has more than max_pending_reads pipelined read commands queued and waiting to be processed.
Language support: Verilog HDL