Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

16.2.1.26. set_instruction_readra()

Prototype:

void set_instruction_readra()

Arguments:

Verilog HDL: logic enable

VHDL: logic enable, bfm_id, req_if(bfm_id)

Returns:

void

Description:

Sets the instruction register file read a value.
Language support: Verilog HDL, VHDL