Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

6.4.34. set_response_latency()

Prototype:

void set_response_latency(bit [31:0]latency, int index)

Arguments:

Verilog HDL: latency, index

VHDL: latency, index, bfm_id, req_if(bfm_id)

Returns:

void

Description:

Sets the response latency for read commands. The response is driven latency number of cycles after receiving the read command.

Designs that set USE_READDATAVALID to 1, cannot set the response latency to 0. For read burst commands the following algorithm determines the read latency:

  • If there are no pending read responses for prior read commands, the response latency is counted from the cycle that the read command is accepted. The read is accepted when the read command is asserted and waitrequest is deasserted.
  • If there are pending responses for prior read commands, the response latency is counted from the cycle in which the read command is presented. The read command is presented when the read command is asserted even if waitrequest is asserted.
Language support: Verilog HDL, VHDL