Visible to Intel only — GUID: nik1412471678991
Ixiasoft
Visible to Intel only — GUID: nik1412471678991
Ixiasoft
7.2. Avalon-MM Monitor Assertion Checking API
By default all assertions are enabled. However, depending on the parameterization of the Avalon-MM interface, some assertions are automatically disabled. For example, you might have to turn off some assertion checking to avoid the monitors generating error messages when injecting protocol errors. Protocol errors are typically injected to test the Avalon-MM component’s error handling capability.
The names of all methods that enable assertions begin with set_enable_a. By default, if your testbench includes the Avalon-MM monitor, the checking function is enabled. You can disable checking with the DISABLE_ALTERA_AVALON_SIM_SVA macro.
- set_enable_a_address_align_with_data_width()
- set_enable_a_beginbursttransfer_exist()
- set_enable_a_beginbursttransfer_legal()
- set_enable_a_beginbursttransfer_single_cycle()
- set_enable_a_begintransfer_exist()
- set_enable_a_begintransfer_legal()
- set_enable_a_begintransfer_single_cycle()
- set_enable_a_burst_legal()
- set_enable_a_byteenable_legal()
- set_enable_a_constant_during_burst()
- set_enable_a_constant_during_clk_disabled()
- set_enable_a_constant_during_waitrequest()
- set_enable_a_exclusive_read_write()
- set_enable_a_half_cycle_reset_legal()
- set_enable_a_less_than_burstcount_max_size()
- set_enable_a_less_than_maximumpendingreadtransactions()
- set_enable_a_no_readdatavalid_during_reset()
- set_enable_a_no_read_during_reset()
- set_enable_a_no_write_during_reset()
- set_enable_a_readid_sequence()
- set_enable_a_read_response_sequence()
- set_enable_a_read_response_timeout()
- set_enable_a_register_incoming_signals()
- set_enable_a_waitrequest_during_reset()
- set_enable_a_waitrequest_timeout()
- set_enable_a_write_burst_timeout()
- set_enable_a_writeid_sequence()
- Coverage Group
- Transaction Monitoring