Avalon Verification IP Suite: User Guide

ID 683439
Date 2/17/2022
Public
Document Table of Contents

9.4.14. set_ready()

Prototype:

set_ready()

Arguments:

Verilog HDL: read_bit

VHDL: read_bit, bfm_id, req_if(bfm_id)

Returns:

void

Description:

Sets the value of the interface’s ready signal. To assert back pressure, deassert this signal. The parameter USE_READY must be set to 1 to enable the ready signal.
Language support: Verilog HDL, VHDL