2024.10.21 |
24.2 |
Updated the legal values for MLAB/M20K for What is the width of a byte for byte enables? parameter for Parameter Settings: Clks/Rd, Byte En in the RAM: 2-PORT Intel® FPGA IP Parameter Settings table. |
2024.07.08 |
24.2 |
- Added Read-During-Write topic.
- Updated the description for sclr and aclr ports in the Input and Output Ports Description table.
- Updated the description for lpm_hint in the FIFO Parameters table.
- Removed mentions of Stratix® 10 in the following (editorial edits to the text only; no change in the technical information):
- The description for wrreq port in the Input and Output Ports Description table.
- The note in the FIFO Synchronous Clear and Asynchronous Clear Effect topic.
- The footnote for Effects on the q output for normal output modes mode in the Asynchronous Clear in DCFIFO table.
- The Guidelines for Embedded Memory ECC Feature topic.
- The Reset Scheme topic.
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2024.03.29 |
23.2 |
Changed DISABLE_EMBEDDED_TIMING_CONSTRAINT to DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT for lpm_hint parameter in the FIFO Parameter Settings. |
2023.12.21 |
23.2 |
- Updated the description for the Using the FIFO parameter editor method in Table Configuration Methods for clarity.
- Added a new topic: Reducing the DCFIFO Depth.
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2023.10.19 |
23.2 |
Updated Coherent Read Memory topic to replace the mention of "Wide simple dual-port" with "Simple dual-port with more than 20-bit wide data". |
2023.06.26 |
23.2 |
- Updated Table: FIFO2 Intel® FPGA IP Current Release Information.
- Added Consider Registering the Memory Output topic.
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2022.09.26 |
22.3 |
- Added Resource and Timing Optimization Feature in MLAB Blocks topic.
- Added Consider the Memory Depth Setting topic.
- Updated the description for Same-Port Read-During-Write Mode and Mixed-Port Read-During-Write Mode.
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2022.04.25 |
21.4 |
Updated the description for True Dual Port Dual Clock Emulator topic. |
2022.01.12 |
21.4 |
Added a note for operation modes support in Stratix® 10 Embedded Memory Features topic. |
2021.10.01 |
20.3 |
- Updated "X" Propagation Support in Simulation.
- Updated Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO.
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2021.09.20 |
20.3 |
- Updated the following topics:
- Read/Write Clock
- Input/Output Clock
- Updated the description for Dual clock: use separate ‘input’ and ‘output’ clocks in Tables: RAM: 1-PORT Intel® FPGA IP Parameter Settings and RAM: 2-PORT Intel® FPGA IP Parameter Settings.
- Updated the description in Reset Scheme for clarity.
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2021.06.11 |
20.3 |
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2021.03.29 |
20.3 |
- Updated the data bits written in Table: Byte Enable Controls in ×40 Data Width (M20K).
- Updated the Stratix® 10 Embedded Memory IP References to include information about inferring memory functions from HDL code.
- Updated the following tables:
- Mixed Port Read-During-Write Output Behaviors
- RAM: 2-PORT Intel® FPGA IP Parameter Settings
- RAM: 2-PORT Intel® FPGA IP Parameter Settings
- RAM: 4-PORT Intel® FPGA IP Parameter Settings
- ROM: 1-PORT Intel® FPGA IP Parameter Settings
- ROM: 2-PORT Intel® FPGA IP Parameter Settings
- eSRAM Intel® FPGA IP Parameter Editor: General Tab
- FIFO Intel® FPGA IP Parameter Settings
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2020.12.14 |
20.3 |
- Added eSRAM Intel® FPGA IP information in Table: Stratix® 10 Memory IPs.
- Updated the description in the Gray-Code Counter Transfer at the Clock Domain Crossing topic of the FIFO Intel® FPGA IP section.
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2020.11.23 |
20.3 |
Updated Table: Shift Register (RAM-based) Intel® FPGA IP Parameter Settings to include information about Create a synchronous clear port. |
2020.11.13 |
20.3 |
Updated the footnotes for aclr (synchronize with read clock) mode in Table: Asynchronous Clear in DCFIFO. |
2020.10.12 |
20.3 |
- Added the "X" Propagation Support in Simulation topic to describe about input signals supporting "X" value in simulation.
- Added the Avoid Changing Clock Signals and Other Memory Signals Simultaneously topic to the Stratix® 10 Embedded Memory Design Considerations section.
- Added the Shift Register (RAM-based) Intel FPGA IP section.
- Removed the Do not analyze the timing between write and read operation. Metastability issues are prevented by never writing and reading at the same address at the same time. parameter from the following tables:
- Mixed Port Read-During-Write Output Behaviors
- RAM: 2-PORT Intel® FPGA IP Parameter Settings
- Updated the following parameter settings tab names in Table: RAM: 2-PORT Intel® FPGA IP Parameters Description:
- Output 1 to Mixed Port Read-During-Write
- Output 2 to Same Port Read-During-Write
- Updated Tables: RAM: 1-PORT Intel® FPGA IP Parameters Description and RAM: 2-PORT Intel® FPGA IP Parameters Description to remove support for Use Stratix M512 emulation logic cell style for the LCs memory block type.
- Updated the MLAB values for What is the width of a byte for byte enables? in Table: RAM: 1-PORT Intel® FPGA IP Parameters Description.
- Updated Table: eSRAM Intel® FPGA IP Parameter Editor: General Tab to update the description for Enable Low Power Mode.
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2020.08.03 |
20.1 |
- Updated Table: Embedded Memory Capacity and Distribution in Stratix® 10 Devices to add resource counts for device GX 1660, GX 2110, GX 10M, TX 850, DX 1100, DX 2100, and DX2800.
- Added a new topic to the Stratix® 10 Embedded Memory Design Considerations section—Including the Reset Release Intel® FPGA IP in Your Design.
- Updated the True Dual Port Dual Clock Emulator section.
- Updated Figure: Mixed-Port Read-During-Write: New_a_old_b Mode.
- Updated the On Chip Memory RAM and ROM Intel® FPGA IPs section.
- Updated the descriptions for the following parameters in Table: RAM: 1-PORT Intel® FPGA IP Parameters:
- Create an ‘aclr’ asynchronous clear for the registered ports
- Create an ‘sclr’ synchronous clear for the registered ports
- Updated the description for clock0 in Table: Interface Signals of the Stratix® 10 RAM and ROM Intel® FPGA IP Cores.
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2019.11.19 |
19.1 |
- Updated Table: Mixed Port Read-During-Write Output Behaviors:
- Updated the Output Data when Read-During-Write value of the constrained_dont_care and dont_care parameters from "New data" to "Don't care".
- Added a footnote to state that the output data is "don't care" because the IP does not guarantee metastability for the output data when read-during-write.
- Updated the FIFO Intel® FPGA IP section.
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2019.10.17 |
19.1 |
- Added new Topic—Avoid Providing Non-Deterministic Input.
- Added a note to the RAM and ROM Interface Signals topic.
- Updated the description for refclk signal in Table: eSRAM Intel® FPGA IP Input and Output Signals.
- Updated Table: Stratix® 10 Memory IP Cores.
- Updated Table: RAM: 2-PORT Intel® FPGA IP Parameter Settings:
- Updated the legal values and description for What clocking method would you like to use?.
- Updated the description for Enable Error Correction Check (ECC).
- Updated Table: Parameters for altera_syncram.
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2019.08.15 |
19.1 |
- Updated the legal values and description for the What should the ‘q’ output be when reading from a memory location being written to? parameter in Table: RAM: 1-PORT Intel® FPGA IP Parameters Description.
- Updated the description for the Get x’s for write masked bytes instead of old data when byte enable is used parameter in Table: RAM: 1-PORT Intel® FPGA IP Parameters Description.
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2019.04.01 |
19.1 |
- Updated the Byte Enable in Stratix® 10 Embedded Memory Blocks topic.
- Updated Table: Byte Enable Controls in ×40 Data Width (M20K).
- Updated the Customize Read-During-Write Behavior topic.
- Updated the description for M20K blocks in the Memory Blocks Error Correction Code Support topic.
- Updated Table: RAM: 2-PORT Intel® FPGA IP Parameter Settings to add notes to the Use clock enable for output registers (Clock Enables) and q_a port (Sclr Options) options.
- Updated Table: RAM: 1-PORT Intel® FPGA IP Parameters Settings:
- Added notes to the Use clock enable for output registers (Clock Enables) and q_a port (Sclr Options) options.
- Updated the legal values and description for the Set the maximum block depth to parameter.
- Updated Table: RAM: 2-PORT Intel® FPGA IP Parameters Settings to update the legal values for the Set the maximum block depth to parameter.
- Updated Table: RAM: 4-PORT Intel® FPGA IP Parameters Settings to update the legal values for the Set the maximum block depth to parameter.
- Made editorial and typographical updates throughout the document.
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2018.12.24 |
18.1 |
- Added a FIFO and FIFO2 Simulation Design Example section.
- Updated the note in the True Dual Ports Dual Clock Emulator topic.
- Added a note to Consider the Memory Block Selection topic.
- Updated the Changing Parameter Settings Manually topic.
- Made minor topic restructuring to the Intel Stratix 10 Embedded Memory Architecture and Features and the On Chip Memory RAM and ROM Intel FPGA IP Cores sections.
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2018.10.24 |
18.1 |
- Added a new topic: Initial Value of Read and Write Address Registers.
- Updated True Dual Ports Dual Clock Emulator topic:
- Updated the description for this topic.
- Updated Table: Differences between Intel Arria 10 TDP Dual Clock Mode and Intel Stratix 10 Emulated TDP Dual Clock Mode to correct the device support for sclr.
- Updated the following figures:
- Output Condition of Port A
- Output Condition of Port B
- Read-During-Write Condition of Port A
- Read-During-Write Condition of Port B
- Renamed topic title Hardware Behavior to Consider the Concurrent Read Behavior.
- Updated the following tables:
- Intel Stratix 10 Embedded Memory Features
- Embedded Memory Capacity and Distribution in Intel Stratix 10 Devices
- RAM: 2-PORT Intel FPGA IP Parameter Settings
- RAM: 4-PORT Intel FPGA IP Parameter Settings
- ROM: 1-PORT Intel FPGA IP Parameter Settings
- ROM: 2-PORT Intel FPGA IP Parameter Settings
- Interface Signals of the Intel Stratix 10 RAM and ROM Intel FPGA IP Cores
- Made minor editorial updates throughout the document.
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