Stratix® 10 Embedded Memory User Guide

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ID 683423
Date 10/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 Embedded Memory Overview 2. Stratix® 10 Embedded Memory Architecture and Features 3. Stratix® 10 Embedded Memory Design Considerations 4. Stratix® 10 Embedded Memory IP References 5. Intel Stratix 10 Embedded Memory Design Example 6. Stratix® 10 Embedded Memory User Guide Archives 7. Document Revision History for the Stratix® 10 Embedded Memory User Guide
1. Stratix® 10 Embedded Memory Overview x
1.1. Stratix® 10 Embedded Memory Features
2. Stratix® 10 Embedded Memory Architecture and Features x
2.1. Byte Enable in Stratix® 10 Embedded Memory Blocks 2.2. Address Clock Enable Support 2.3. Asynchronous Clear and Synchronous Clear 2.4. Memory Blocks Error Correction Code (ECC) Support 2.5. Force-to-Zero 2.6. Coherent Read Memory 2.7. Freeze Logic 2.8. True Dual Port Dual Clock Emulator 2.9. 'X' Propagation Support in Simulation 2.10. Stratix® 10 Supported Embedded Memory IPs 2.11. Stratix® 10 Embedded Memory Clocking Modes 2.12. Stratix® 10 Embedded Memory Configurations 2.13. Initial Value of Read and Write Address Registers
2.1. Byte Enable in Stratix® 10 Embedded Memory Blocks x
2.1.1. Byte Enable Controls 2.1.2. Data Byte Output 2.1.3. Byte Enable Behavior
2.4. Memory Blocks Error Correction Code (ECC) Support x
2.4.1. Parity Bit 2.4.2. ECC Parity Flip 2.4.3. ECC Read-During-Write Behavior 2.4.4. Error Correction Code Truth Table
2.6. Coherent Read Memory x
2.6.1. Forwarding Logic
2.8. True Dual Port Dual Clock Emulator x
2.8.1. Reducing the DCFIFO Depth
2.11. Stratix® 10 Embedded Memory Clocking Modes x
2.11.1. Single Clock Mode 2.11.2. Read/Write Clock Mode 2.11.3. Input/Output Clock Mode 2.11.4. Asynchronous/Synchronous Clears in Clocking Modes 2.11.5. Output Read Data in Simultaneous Read/Write 2.11.6. Independent Clock Enables in Clocking Modes
2.12. Stratix® 10 Embedded Memory Configurations x
2.12.1. Mixed-Width Port Configurations
3. Stratix® 10 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Read Behavior 3.3. Read-During-Write (RDW) 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Including the Reset Release Intel® FPGA IP in Your Design 3.9. Resource and Timing Optimization Feature in MLAB Blocks 3.10. Consider the Memory Depth Setting 3.11. Consider Registering the Memory Output
3.3. Read-During-Write (RDW) x
3.3.1. Customize Read-During-Write Behavior
3.3.1. Customize Read-During-Write Behavior x
3.3.1.1. Same-Port Read-During-Write Mode 3.3.1.2. Mixed-Port Read-During-Write Mode
4. Stratix® 10 Embedded Memory IP References x
4.1. On Chip Memory RAM and ROM Intel® FPGA IPs 4.2. eSRAM Intel® FPGA IP 4.3. FIFO Intel® FPGA IP 4.4. FIFO2 Intel® FPGA IP 4.5. Shift Register (RAM-based) Intel® FPGA IP
4.1. On Chip Memory RAM and ROM Intel® FPGA IPs x
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs 4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters 4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters 4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters 4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters 4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters 4.1.7. RAM and ROM Interface Signals 4.1.8. Changing Parameter Settings Manually
4.1.8. Changing Parameter Settings Manually x
4.1.8.1. RAM and ROM Parameter Settings
4.2. eSRAM Intel® FPGA IP x
4.2.1. Release Information for eSRAM Intel® FPGA IP 4.2.2. eSRAM System Features 4.2.3. eSRAM Intel® FPGA IP Parameters 4.2.4. eSRAM Intel® FPGA IP Interface Signals 4.2.5. eSRAM Intel® FPGA IP Simulation Walk-Through 4.2.6. eSRAM Timing Diagrams
4.2.2. eSRAM System Features x
4.2.2.1. eSRAM Specifications 4.2.2.2. eSRAM Usage Model
4.3. FIFO Intel® FPGA IP x
4.3.1. Release Information for FIFO Intel® FPGA IP 4.3.2. Configuration Methods 4.3.3. Specifications 4.3.4. FIFO Functional Timing Requirements 4.3.5. SCFIFO ALMOST_EMPTY Functional Timing 4.3.6. FIFO Output Status Flag and Latency 4.3.7. FIFO Metastability Protection and Related Options 4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect 4.3.9. SCFIFO and DCFIFO Show-Ahead Mode 4.3.10. Different Input and Output Width 4.3.11. DCFIFO Timing Constraint Setting 4.3.12. Coding Example for Manual Instantiation 4.3.13. Design Example 4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing 4.3.15. Guidelines for Embedded Memory ECC Feature 4.3.16. FIFO Intel® FPGA IP Parameters 4.3.17. Reset Scheme
4.3.3. Specifications x
4.3.3.1. Verilog HDL Prototype 4.3.3.2. VHDL Component Declaration 4.3.3.3. VHDL LIBRARY-USE Declaration 4.3.3.4. FIFO Signals 4.3.3.5. FIFO Parameter Settings
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.3.8.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.3.11. DCFIFO Timing Constraint Setting x
4.3.11.1. Embedded Timing Constraint 4.3.11.2. User Configurable Timing Constraint
4.3.11.2. User Configurable Timing Constraint x
4.3.11.2.1. SDC Commands
4.4. FIFO2 Intel® FPGA IP x
4.4.1. Release Information for FIFO2 Intel® FPGA IP 4.4.2. Configuration Methods 4.4.3. Fmax Target Measuring Methodology 4.4.4. Performance Considerations 4.4.5. FIFO2 Intel® FPGA IP Features 4.4.6. FIFO2 Intel® FPGA IP Parameters 4.4.7. FIFO2 Intel® FPGA IP Interface Signals 4.4.8. Reset and Clock Schemes
4.4.5. FIFO2 Intel® FPGA IP Features x
4.4.5.1. FIFO2 Specifications
4.4.6. FIFO2 Intel® FPGA IP Parameters x
4.4.6.1. FIFO2 Parameter Settings
4.4.7. FIFO2 Intel® FPGA IP Interface Signals x
4.4.7.1. SCFIFO Signals 4.4.7.2. DCFIFO Signals
4.4.8. Reset and Clock Schemes x
4.4.8.1. Clock Domains 4.4.8.2. Reset
4.4.8.2. Reset x
4.4.8.2.1. FIFO2 Intel® FPGA IP Reset Guidelines
4.5. Shift Register (RAM-based) Intel® FPGA IP x
4.5.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP 4.5.2. Shift Register (RAM-based) Intel® FPGA IP Features 4.5.3. Shift Register (RAM-based) Intel® FPGA IP General Description 4.5.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings 4.5.5. Shift Register Ports and Parameters Setting
5. Intel Stratix 10 Embedded Memory Design Example x
5.1. FIFO and FIFO2 Design Example
5.1. FIFO and FIFO2 Design Example x
5.1.1. Generating the Design Example 5.1.2. Simulating the Design Example
5.1.2. Simulating the Design Example x
5.1.2.1. Simulation Results
1. Stratix® 10 Embedded Memory Overview
2. Stratix® 10 Embedded Memory Architecture and Features
3. Stratix® 10 Embedded Memory Design Considerations
4. Stratix® 10 Embedded Memory IP References
5. Intel Stratix 10 Embedded Memory Design Example
6. Stratix® 10 Embedded Memory User Guide Archives
7. Document Revision History for the Stratix® 10 Embedded Memory User Guide

4.1.8.1. RAM and ROM Parameter Settings

Table 29.   Parameters for altera_syncram Use the parameter list when editing the design file manually.
Name Legal Values Description
operation_mode

SINGLE_PORT

DUAL_PORT

BIDIR_DUAL_PORT

QUAD_PORT

ROM

Operation mode of the memory block.
width_a — Data width of port A.
widthad_a — Address width of port A.
widthad2_a   Address 2 width of port A.
numwords_a — Number of data words in the memory block for port A.
outdata_reg_a

UNREGISTERED

CLOCK1

CLOCK0

Clock for the data output registers of port A.
outdata_aclr_a

NONE

CLEAR1

CLEAR0

Asynchronous clear for data output registers of port A. When the outdata_reg_a parameter is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch.
outdata_sclr_a

NONE

SCLEAR

Synchronous clear for data output registers of port A. When the outdata_reg_a parameter is set to NONE, this parameter specifies the clearing parameter for the output latch.
address_aclr_a

NONE

Option to clear the address input registers of port A.
width_byteena_a — Width of the byte-enable bus of port A. The width must be equal to the value of width_a divided by the byte size. The default value of 1 is only allowed when byte-enable is not used.
width_b — Data width of port B.
widthad_b — Address width of port B.
widthad2_b — Address 2 width of port B.
numwords_b — Number of data words in the memory block for port B.
outdata_reg_b

UNREGISTERED

CLOCK1

CLOCK0

Clock for the data output registers of port B.
indata_reg_b

CLOCK1

CLOCK0

Clock for the data input registers of port B.
address_reg_b

CLOCK1

CLOCK0

Clock for the address registers of port B.
byteena_reg_b

CLOCK1

CLOCK0

Clock for the byte-enable registers of port B.
outdata_aclr_b

NONE

CLEAR1

CLEAR0

Asynchronous clear for data output registers of port B. When the outdata_reg_b parameter is set to UNREGISTERED, this parameter specifies the clearing parameter for the output latch.
outdata_sclr_b

NONE

SCLEAR

Synchronous clear for data output registers of port B. When the outdata_reg_b parameter is set to NONE, this parameter specifies the clearing parameter for the output latch.
address_aclr_b

NONE

Option to clear the address input registers of port B.
width_byteena_b — Width of the byte-enable bus of port B. The width must be equal to the value of width_b divided by the byte size. The default value of 1 is only allowed when byte-enable is not used.
intended_device_family

“Stratix 10”

Parameter used for simulation purpose.
ram_block_type

AUTO

M20K

MLAB

The memory block type.
byte_size

5

8

9

10

The byte size for the byte-enable mode.
read_during_write_mode_mixed_ports

DONT_CARE

CONSTRAINT_DONT_CARE

NEW_DATA

OLD_DATA

NEW_A_OLD_B

The behavior for the read-during-write mode.
  • The default value is DONT_CARE.
  • The value of NEW_DATA is supported only when the read address and output data are registered by the write clock in the LUTRAM mode.
  • The value of CONSTRAINED_DONT_CARE is supported only in the LUTRAM mode.
  • The value of NEW_A_OLD_B is supported only when the operation_mode parameter is set to QUAD_PORT.
init_file

*.mif

*.hex

The initialization file.
init_file_layout

PORT_A

PORT_B 		The layout of the initialization file.
maximum_depth — The depth of the memory block slices.
clock_enable_input_a

NORMAL

BYPASS

The clock enable for the input registers of port A.
clock_enable_output_a

NORMAL

BYPASS

The clock enable for the output registers of port A.
clock_enable_input_b

NORMAL

BYPASS

The clock enable for the input registers of port B.
clock_enable_output_b

NORMAL

BYPASS

The clock enable for the output registers of port B.
read_during_write_mode_port_a

NEW_DATA_NO_NBE_READ

NEW_DATA_WITH_NBE_READ

OLD_DATA

DONT_CARE

The read-during-write behavior for port A.
read_during_write_mode_port_b

NEW_DATA_NO_NBE_READ

NEW_DATA_WITH_NBE_READ

OLD_DATA

DONT_CARE

The read-during-write behavior for port B.
enable_ecc

TRUE

FALSE

Enables or disables the ECC feature.
ecc_pipeline_stage_enabled

TRUE

FALSE

  • Specifies whether to enable ECC Pipeline Registers before the output decoder to achieve the same performance as non-ECC mode at the expense of one cycle of latency.
  • The parameter enable_ecc must set to TRUE if this parameter is set to TRUE.
  • The parameter outdata_reg_b cannot set to UNREGISTERED if this parameter is set to TRUE.
  • The default value is FALSE.
enable_ecc_encoder_bypass

TRUE

FALSE

Enables or disables the ECC Encoder Bypass feature.
  • The parameter enable_ecc must set to TRUE if this parameter is set to TRUE.
enable_coherent_read

TRUE

FALSE

Enables or disables the coherent read feature.
  • The default value is FALSE.
enable_force_to_zero

TRUE

FALSE

Enables or disables the Force-to-Zero feature.
  • The default value is FALSE.
width_eccencparity 8 The width of the eccencparity signal.
optimization_option

AUTO

Specifies how the RAM block would be optimized.
  • If AUTO is selected, the fitter determines whether the RAM block is in High_Speed or Low_Power mode.
  • The RAM block type must be M20K when High_Speed or Low_Power is selected.
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