1.5. Intel® Stratix® 10 MX Family Plan
Intel® Stratix® 10 MX Device Name |
Logic Elements (KLE) |
eSRAM Blocks | eSRAM Mbits | M20K Blocks |
M20K Mbits |
MLAB Counts |
MLAB Mbits |
18x19 Multipliers 1 |
HPS Quad Core |
---|---|---|---|---|---|---|---|---|---|
MX 1650 | 1679 | 2 | 94.5 | 6,162 | 120 | 14,230 | 9 | 6,652 | — |
MX 2100 | 2073 | 2 | 94.5 | 6,847 | 134 | 17,568 | 11 | 7,920 | — |
|
Stratix 10 MX Device Name |
F1760 NF43 (42.5x42.5 mm2) |
F2597 NF53/UF53 (52.5x52.5 mm2) |
F2912 UF55 (55x55 mm2) |
---|---|---|---|
MX 2100 | N/A | 640, 16, 312, 48 8, 512, tile layout 1 |
N/A |
MX 1650 | N/A | 656, 32, 312, 96 8, 512, tile layout 2 |
584, 8, 288, 96 8, 512, tile layout 4 |
MX 2100 | N/A | 656, 32, 312, 96 8, 512, tile layout 2 |
584, 8, 288, 96 8, 512, tile layout 4 |
MX 1650 | N/A | 656, 32, 312, 96 16, 512, tile layout 3 |
N/A |
MX 2100 | N/A | 656, 32, 312, 96 16, 512, tile layout 3 |
N/A |
Figure 2. Tile Layout 1: Intel® Stratix® 10 MX Device with 2 H-Tiles (48 Transceiver Channels) and Two 4 GByte HBM2
Figure 3. Tile Layout 2: Intel® Stratix® 10 MX Device with 4 H-Tiles (96 Transceiver Channels) and Two 4 GByte HBM2
Figure 4. Tile Layout 3: Intel® Stratix® 10 MX Device with 4 H-Tiles (96 Transceiver Channels) and Two 8 GByte HBM2
Figure 5. Tile Layout 4: Intel® Stratix® 10 MX Device with 3 E-Tiles, 1 H-Tile (96 Transceiver Channels) and Two 4 GByte HBM2
1 The number of 27x27 multipliers is one-half the number of 18x19 multipliers.
2 All packages are ball grid arrays with 1.0 mm pitch.
3 High-Voltage I/O pins are used for 3 V and 2.5 V interfacing.
4 Each LVDS pair can be configured as either a differential input or a differential output.
5 High-Voltage I/O pins and LVDS pairs are included in the General Purpose I/O count. Transceivers are counted separately.
6 Each package column offers pin migration (common circuit board footprint) for all devices in the column.