Visible to Intel only — GUID: iff1660546493627
Ixiasoft
Visible to Intel only — GUID: iff1660546493627
Ixiasoft
3.9. Resource and Timing Optimization Feature in MLAB Blocks
The Stratix® 10 embedded memory block allow users to access two different read addresses from a physical MLAB cell. With this feature, only one MLAB block is used to read two separate addresses, improving the timing performance and optimizing user design in terms of logic elements. This feature is available by default in all Stratix® 10 devices; when MLAB is directly instantiated via atom.