Stratix® 10 Embedded Memory User Guide

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ID 683423
Date 10/21/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 Embedded Memory Overview 2. Stratix® 10 Embedded Memory Architecture and Features 3. Stratix® 10 Embedded Memory Design Considerations 4. Stratix® 10 Embedded Memory IP References 5. Intel Stratix 10 Embedded Memory Design Example 6. Stratix® 10 Embedded Memory User Guide Archives 7. Document Revision History for the Stratix® 10 Embedded Memory User Guide
1. Stratix® 10 Embedded Memory Overview x
1.1. Stratix® 10 Embedded Memory Features
2. Stratix® 10 Embedded Memory Architecture and Features x
2.1. Byte Enable in Stratix® 10 Embedded Memory Blocks 2.2. Address Clock Enable Support 2.3. Asynchronous Clear and Synchronous Clear 2.4. Memory Blocks Error Correction Code (ECC) Support 2.5. Force-to-Zero 2.6. Coherent Read Memory 2.7. Freeze Logic 2.8. True Dual Port Dual Clock Emulator 2.9. 'X' Propagation Support in Simulation 2.10. Stratix® 10 Supported Embedded Memory IPs 2.11. Stratix® 10 Embedded Memory Clocking Modes 2.12. Stratix® 10 Embedded Memory Configurations 2.13. Initial Value of Read and Write Address Registers
2.1. Byte Enable in Stratix® 10 Embedded Memory Blocks x
2.1.1. Byte Enable Controls 2.1.2. Data Byte Output 2.1.3. Byte Enable Behavior
2.4. Memory Blocks Error Correction Code (ECC) Support x
2.4.1. Parity Bit 2.4.2. ECC Parity Flip 2.4.3. ECC Read-During-Write Behavior 2.4.4. Error Correction Code Truth Table
2.6. Coherent Read Memory x
2.6.1. Forwarding Logic
2.8. True Dual Port Dual Clock Emulator x
2.8.1. Reducing the DCFIFO Depth
2.11. Stratix® 10 Embedded Memory Clocking Modes x
2.11.1. Single Clock Mode 2.11.2. Read/Write Clock Mode 2.11.3. Input/Output Clock Mode 2.11.4. Asynchronous/Synchronous Clears in Clocking Modes 2.11.5. Output Read Data in Simultaneous Read/Write 2.11.6. Independent Clock Enables in Clocking Modes
2.12. Stratix® 10 Embedded Memory Configurations x
2.12.1. Mixed-Width Port Configurations
3. Stratix® 10 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Read Behavior 3.3. Read-During-Write (RDW) 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Including the Reset Release Intel® FPGA IP in Your Design 3.9. Resource and Timing Optimization Feature in MLAB Blocks 3.10. Consider the Memory Depth Setting 3.11. Consider Registering the Memory Output
3.3. Read-During-Write (RDW) x
3.3.1. Customize Read-During-Write Behavior
3.3.1. Customize Read-During-Write Behavior x
3.3.1.1. Same-Port Read-During-Write Mode 3.3.1.2. Mixed-Port Read-During-Write Mode
4. Stratix® 10 Embedded Memory IP References x
4.1. On Chip Memory RAM and ROM Intel® FPGA IPs 4.2. eSRAM Intel® FPGA IP 4.3. FIFO Intel® FPGA IP 4.4. FIFO2 Intel® FPGA IP 4.5. Shift Register (RAM-based) Intel® FPGA IP
4.1. On Chip Memory RAM and ROM Intel® FPGA IPs x
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs 4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters 4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters 4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters 4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters 4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters 4.1.7. RAM and ROM Interface Signals 4.1.8. Changing Parameter Settings Manually
4.1.8. Changing Parameter Settings Manually x
4.1.8.1. RAM and ROM Parameter Settings
4.2. eSRAM Intel® FPGA IP x
4.2.1. Release Information for eSRAM Intel® FPGA IP 4.2.2. eSRAM System Features 4.2.3. eSRAM Intel® FPGA IP Parameters 4.2.4. eSRAM Intel® FPGA IP Interface Signals 4.2.5. eSRAM Intel® FPGA IP Simulation Walk-Through 4.2.6. eSRAM Timing Diagrams
4.2.2. eSRAM System Features x
4.2.2.1. eSRAM Specifications 4.2.2.2. eSRAM Usage Model
4.3. FIFO Intel® FPGA IP x
4.3.1. Release Information for FIFO Intel® FPGA IP 4.3.2. Configuration Methods 4.3.3. Specifications 4.3.4. FIFO Functional Timing Requirements 4.3.5. SCFIFO ALMOST_EMPTY Functional Timing 4.3.6. FIFO Output Status Flag and Latency 4.3.7. FIFO Metastability Protection and Related Options 4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect 4.3.9. SCFIFO and DCFIFO Show-Ahead Mode 4.3.10. Different Input and Output Width 4.3.11. DCFIFO Timing Constraint Setting 4.3.12. Coding Example for Manual Instantiation 4.3.13. Design Example 4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing 4.3.15. Guidelines for Embedded Memory ECC Feature 4.3.16. FIFO Intel® FPGA IP Parameters 4.3.17. Reset Scheme
4.3.3. Specifications x
4.3.3.1. Verilog HDL Prototype 4.3.3.2. VHDL Component Declaration 4.3.3.3. VHDL LIBRARY-USE Declaration 4.3.3.4. FIFO Signals 4.3.3.5. FIFO Parameter Settings
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.3.8.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.3.11. DCFIFO Timing Constraint Setting x
4.3.11.1. Embedded Timing Constraint 4.3.11.2. User Configurable Timing Constraint
4.3.11.2. User Configurable Timing Constraint x
4.3.11.2.1. SDC Commands
4.4. FIFO2 Intel® FPGA IP x
4.4.1. Release Information for FIFO2 Intel® FPGA IP 4.4.2. Configuration Methods 4.4.3. Fmax Target Measuring Methodology 4.4.4. Performance Considerations 4.4.5. FIFO2 Intel® FPGA IP Features 4.4.6. FIFO2 Intel® FPGA IP Parameters 4.4.7. FIFO2 Intel® FPGA IP Interface Signals 4.4.8. Reset and Clock Schemes
4.4.5. FIFO2 Intel® FPGA IP Features x
4.4.5.1. FIFO2 Specifications
4.4.6. FIFO2 Intel® FPGA IP Parameters x
4.4.6.1. FIFO2 Parameter Settings
4.4.7. FIFO2 Intel® FPGA IP Interface Signals x
4.4.7.1. SCFIFO Signals 4.4.7.2. DCFIFO Signals
4.4.8. Reset and Clock Schemes x
4.4.8.1. Clock Domains 4.4.8.2. Reset
4.4.8.2. Reset x
4.4.8.2.1. FIFO2 Intel® FPGA IP Reset Guidelines
4.5. Shift Register (RAM-based) Intel® FPGA IP x
4.5.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP 4.5.2. Shift Register (RAM-based) Intel® FPGA IP Features 4.5.3. Shift Register (RAM-based) Intel® FPGA IP General Description 4.5.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings 4.5.5. Shift Register Ports and Parameters Setting
5. Intel Stratix 10 Embedded Memory Design Example x
5.1. FIFO and FIFO2 Design Example
5.1. FIFO and FIFO2 Design Example x
5.1.1. Generating the Design Example 5.1.2. Simulating the Design Example
5.1.2. Simulating the Design Example x
5.1.2.1. Simulation Results
1. Stratix® 10 Embedded Memory Overview
2. Stratix® 10 Embedded Memory Architecture and Features
3. Stratix® 10 Embedded Memory Design Considerations
4. Stratix® 10 Embedded Memory IP References
5. Intel Stratix 10 Embedded Memory Design Example
6. Stratix® 10 Embedded Memory User Guide Archives
7. Document Revision History for the Stratix® 10 Embedded Memory User Guide

4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters

This table lists the parameters for the RAM: 2-PORT Intel® FPGA IP.
Table 24.  RAM: 2-PORT Intel® FPGA IP Parameter Settings
Parameter Legal Values Description
Parameter Settings: General
How will you be using the dual port RAM?

Operation mode:

  • With one read port and one write port
  • With two read/write ports
Specifies how you use the dual port RAM.
How do you want to specify the memory size?

Type:

  • As a number of words
  • As a number of bits
Determines whether to specify the memory size in words or bits.
Parameter Settings: Widths/Blk Type
How many words of memory? — Specifies the number of words.
Use different data widths on different ports On/Off Specifies whether to use different data widths on different ports.
When you select With one read port and one write port or With two read/write ports, the following options are available:
  • How wide should the ‘q_a’ output bus be?
  • How wide should the ‘data_a’ input bus be?
  • How wide should the ‘q_b’ output bus be?
 — Specifies the width of the input and output ports.
Ram block type
  • Auto
  • MLAB
  • M20K
  • LCs
Specifies the memory block type. The types of memory block that are available for selection depends on your target device.
Set the maximum block depth to
  • Auto: Auto, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, or 16384
  • MLAB: Auto or 32
  • M20K: Auto, 512, 1024, or 2048
  • LCs: Auto
Specifies the maximum block depth in words.
How should the memory be implemented?
  • Use default logic cell style
Specifies the logic cell implementation method.
  • Select Use default logic cell style if you prefer smaller and faster memory capacity.
Parameter Settings: Clks/Rd, Byte En
Which clocking method do you want to use?
  • Single
  • Dual clock: use separate ‘read’ and ‘write’ clocks
  • Dual clock: use separate ‘input’ and ‘output’ clocks
  • Customize clocks for A and B ports
Specifies the clocking method to use.
  • Single—A single clock and a clock enable controls all registers of the memory block.
  • Dual clock: use separate ‘read’ and ‘write’ clock—A write clock controls the data-input, write-address, and write-enable registers while the read clock controls the data-output, read-address, and read-enable registers.
  • Dual Clock: use separate ‘input’ and ‘output’ clocks—An input clock controls all registers related to the data input to the embedded memory block including data, address, byte enables, read enables, and write enables. An output clock controls the data output registers.
  • Dual clock: use separate clocks for A and B ports—Clock A controls all registers on the port A side; clock B controls all registers on the port B side. Each port also supports independent clock enables for both port A and port B registers, respectively.
  • Customize clocks for A and B ports—To use this option, the Emulate TDP dual clock mode option must also be enabled.
When you select With two read/write ports and Customize clocks for A and B ports clocking method, the following option is available:

Emulate TDP dual clock mode

 On/Off Specifies whether to emulate a TDP dual clock mode. The clock connection to Port A must be a slow clock and the clock connection to Port B must be a fast clock.
When you select With one read port and one write port, the following option is available:

Create a ‘rden’ read enable signal

 On/Off Specifies whether to create a read enable signal for port B.
When you select With two read/write ports, the following option is available:

Create a ‘rden_a’ and ‘rden_b’ read enable signals

 Specifies whether to create a read enable signal for port A and B.
Create byte enable for port A On/Off Specifies whether to create a byte enable for port A and B. Turn on these options if you want to mask the input data so that only specific bytes, nibbles, or bits of data are written.

To enable byte enable for port A and port B, the data width ratio has to be 1 or 2 for the RAM: 1-PORT and RAM: 2-PORT Intel® FPGA IPs.

The option to create a byte enable for port B is only available when you select the With two read/write ports option.

Create byte enable for port B On/Off

What is the width of a byte for byte enables?
  • MLAB/M20K: 5, 8, 9, or 10
  • Other memory block types: 8 or 9
Specifies the width of a byte for byte enables.

This option is only available when you select the Create byte enable for port A and/or Create byte enable for port B option(s).

Enable Error Correction Check (ECC) On/Off Specifies whether to enable the ECC feature that corrects single bit errors, double adjacent bit errors, and triple adjacent bit errors at the output of the memory.
Enable ECC Pipeline Registers On/Off Specifies whether to enable the ECC Pipeline Registers before the output decoder to achieve that same performance as non-ECC mode at the expense of one cycle of latency.
Enable ECC Encoder Bypass On/Off Specifies whether to enable the ECC encoder bypass feature that allows you to selectively insert parity bits into the memory through eccencparity port.
Enable Coherent Read On/Off Specifies whether to enable the coherent read feature to present with coherent memory read. This feature allows you to read out current memory content, perform operation on top of the content, and write back to the same location in the same cycle.
Parameter Settings: Regs/Clkens/Aclrs/Sclrs
Which ports should be registered?

When you select With one read port and one write port, the following options are available:

  • All write input ports
  • raddress port
  • q_b port

When you select With two read/write ports, the following options are available:

  • All write input ports
  • raddress port
  • q_a port
  • q_b port
 On/Off Specifies whether to register the read or write input and output ports.

Clock Enables

When you select With one read port and one write port, the following option is available:

  • Use different clock enables for registers
  • Use clock enable for write input registers
  • Use clock enable for read input registers
  • Use clock enable for output registers

When you select With two read /write ports, the following options are available:

  • Use different clock enables for registers
  • Use clock enable for port A input registers
  • Use clock enable for port A output registers
  • Use clock enable for port B input registers
  • Use clock enable for port B output registers
 On/Off Specifies whether to create clock enables for read and write registers.
Note: For MLAB blocks, a non-deterministic output may be produced in the first clock cycle when you select the Use clock enable for output registers option.

Addressstalls

When you select With one read port and one write port, the following option is available:

  • Create a ‘addressstall_a’ input port.
 On/Off Specifies whether to create clock enables for address registers. You can create these ports to act as an extra active low clock enable input for the address registers.

Aclr Options

When you select With one read port and one write port, the following option is available:

  • q_b port

When you select With two read /write ports, the following options are available:

  • q_a port
  • q_b port
 On/Off

Specifies whether to create an asynchronous clear port for the registered ports. Specifies whether the ‘q_a’ and ‘q_b’ ports are cleared by the aclr port.

Sclr Options

When you select With one read port and one write port, the following option is available:

  • q_b port

When you select With two read/write ports, the following options are available:

  • q_a port
  • q_b port
 On/Off Specifies whether to create a synchronous clear port for the registered ports. Specifies whether the ‘q_a’, and ‘q_b’ ports are cleared by the sclr port.
Note: For MLAB blocks, a non-deterministic output may be produced in the first clock cycle when you select the q_b port option.
Parameter Settings: Mixed Port Read-During-Write (This tab is only applicable when you select With one read port and one write ports)

How should the q_a and q_b outputs behave when reading a memory location that is being written from the other port?
  • New Data
  • Old Data
  • Don't Care

Specifies the output behavior when read-during-write occurs.

  • New Data—New data is available on the rising edge of the same clock cycle on which it was written.
  • Old Data— The RAM outputs reflect the old data at that address before the write operation proceeds.
  • Don't Care—This option functions differently when you turn it on depending on the following memory block type you select:
    • When you set the memory block type to Auto, M20K, or any other block RAM, the RAM outputs ‘don't care’ or “unknown” values for read-during-write operation without analyzing the timing path.
    • When you set the memory block type to MLAB (for LUTRAM), the RAM outputs ‘don't care’ or ‘unknown’ values for read-during-write operation but analyzes the timing path to prevent metastability.
Parameter Settings: Same Port Read-During-Write (This tab is only available when you select With two read/write ports)
What should the ‘q_a’ output be when reading from a memory location being written to?
  • New Data
  • Old Data

Specifies the output behavior when read-during-write occurs.

  • New Data—New data is available on the rising edge of the same clock cycle on which it was written.
  • Old Data—The RAM outputs reflect the old data at that address before the write operation proceeds.
What should the ‘q_b’ output be when reading from a memory location being written to?
Get x’s for write masked bytes instead of old data when byte enable is used On/Off Turn on this option to obtain ‘X’ on the masked byte.
Parameter Settings: Mem Init
Do you want to specify the initial content of the memory?
  • No, leave it blank
  • Yes, use this file for the memory content data

Specifies the initial content of the memory.

To initialize the memory to zero, select No, leave it blank.

To use a memory initialization file (.mif) or a hexadecimal (Altera-format) file (.hex), select Yes, use this file for the memory content data.

Initialize memory content data to XX..X on power-up in simulation On/Off —
The initial content file should conform to which port's dimensions?
  • PORT_A
  • PORT_B
If you select to use the initial content file for memory content data, select the port the file should conform to.
Implement clock-enable circuitry for use in a partial reconfiguration region On/Off

Specifies whether to implement clock-enable circuitry for use in a partial reconfiguration region. Implement clock-enable circuitry for use in a partial reconfiguration region

Parameter Settings: Performance Optimization
Enable Force to Zero On/Off Specifies whether to set the output to zero when you deassert the read enable signal.

Enabling this feature helps improve the glue logic performance when the selected memory depth is larger than a single memory block.

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