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1. Stratix® 10 Embedded Memory Overview
2. Stratix® 10 Embedded Memory Architecture and Features
3. Stratix® 10 Embedded Memory Design Considerations
4. Stratix® 10 Embedded Memory IP References
5. Intel Stratix 10 Embedded Memory Design Example
6. Stratix® 10 Embedded Memory User Guide Archives
7. Document Revision History for the Stratix® 10 Embedded Memory User Guide
2.1. Byte Enable in Stratix® 10 Embedded Memory Blocks
2.2. Address Clock Enable Support
2.3. Asynchronous Clear and Synchronous Clear
2.4. Memory Blocks Error Correction Code (ECC) Support
2.5. Force-to-Zero
2.6. Coherent Read Memory
2.7. Freeze Logic
2.8. True Dual Port Dual Clock Emulator
2.9. 'X' Propagation Support in Simulation
2.10. Stratix® 10 Supported Embedded Memory IPs
2.11. Stratix® 10 Embedded Memory Clocking Modes
2.12. Stratix® 10 Embedded Memory Configurations
2.13. Initial Value of Read and Write Address Registers
3.1. Consider the Memory Block Selection
3.2. Consider the Concurrent Read Behavior
3.3. Read-During-Write (RDW)
3.4. Consider Power-Up State and Memory Initialization
3.5. Reduce Power Consumption
3.6. Avoid Providing Non-Deterministic Input
3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously
3.8. Including the Reset Release Intel® FPGA IP in Your Design
3.9. Resource and Timing Optimization Feature in MLAB Blocks
3.10. Consider the Memory Depth Setting
3.11. Consider Registering the Memory Output
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs
4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters
4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters
4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters
4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters
4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters
4.1.7. RAM and ROM Interface Signals
4.1.8. Changing Parameter Settings Manually
4.3.1. Release Information for FIFO Intel® FPGA IP
4.3.2. Configuration Methods
4.3.3. Specifications
4.3.4. FIFO Functional Timing Requirements
4.3.5. SCFIFO ALMOST_EMPTY Functional Timing
4.3.6. FIFO Output Status Flag and Latency
4.3.7. FIFO Metastability Protection and Related Options
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect
4.3.9. SCFIFO and DCFIFO Show-Ahead Mode
4.3.10. Different Input and Output Width
4.3.11. DCFIFO Timing Constraint Setting
4.3.12. Coding Example for Manual Instantiation
4.3.13. Design Example
4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing
4.3.15. Guidelines for Embedded Memory ECC Feature
4.3.16. FIFO Intel® FPGA IP Parameters
4.3.17. Reset Scheme
4.4.1. Release Information for FIFO2 Intel® FPGA IP
4.4.2. Configuration Methods
4.4.3. Fmax Target Measuring Methodology
4.4.4. Performance Considerations
4.4.5. FIFO2 Intel® FPGA IP Features
4.4.6. FIFO2 Intel® FPGA IP Parameters
4.4.7. FIFO2 Intel® FPGA IP Interface Signals
4.4.8. Reset and Clock Schemes
4.5.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP
4.5.2. Shift Register (RAM-based) Intel® FPGA IP Features
4.5.3. Shift Register (RAM-based) Intel® FPGA IP General Description
4.5.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings
4.5.5. Shift Register Ports and Parameters Setting
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1.1. Stratix® 10 Embedded Memory Features
The Stratix® 10 devices contain the following types of memory blocks: Embedded SRAM (eSRAM) blocks, M20K blocks, and memory logic array blocks (MLABs).
- 47.25-Megabit (Mb) eSRAM blocks
- Fast path, low latency, high bandwidth and very high random transaction rate (RTR) on-chip memory block.
- Each block consists of 8 channels and each channel has 42 banks.
- Each bank is configurable to 2K depth and 72-bit data width.
- Supports only simple dual-port RAM with concurrent read and write access per channel.
- 20-kilobit (Kb) M20K blocks
- Blocks of dedicated memory resources.
- Ideal for larger memory arrays, while providing a large number of independent ports.
- 640-bit MLABs
- Enhanced memory blocks configured from dual-purpose logic array blocks (LABs).
- Ideal for wide and shallow memory arrays.
- Optimized for implementation of shift registers for digital signal processing (DSP) applications, wide and shallow FIFO buffers, and filter delay lines.
- Each MLAB is made up of ten adaptive logic modules (ALMs).
In Stratix® 10 devices, you can configure each ALM in the MLAB as ten 32×2 blocks. The Stratix® 10 devices provide one 32×20 simple dual-port SRAM block per MLAB.
The Stratix® 10 embedded memory blocks support the following operation modes:
- Single-port
- Simple dual-port
- True dual-port
- Simple quad-port
- ROM
Note: Simple Quad-port mode is supported for the -E1V, -E2V and -E3V speed grades of the Intel Stratix 10 devices only.
Features | eSRAM | M20K | MLAB |
---|---|---|---|
Maximum operating frequency | 750 MHz |
|
1 GHz |
Total RAM bits (including parity bits) | 47.25 Mb | 20,480 bits | 640 bits |
Byte enable | N/A | Supported | Supported |
Address clock enable | N/A | Supported (only in simple dual-port RAM mode) | Supported |
Simple dual-port mixed width | N/A | Supported | N/A |
FIFO buffer mixed width | N/A | Supported | N/A |
Memory Initialization File (.mif) | N/A | Supported | Supported |
Dual-clock mode | N/A | Supported (only in simple dual-port RAM mode) | Supported |
Full synchronous memory | N/A | Supported | Supported |
Asynchronous memory | N/A | N/A | Only for flow-through read memory operations |
Power-up state | N/A | Output ports are cleared |
|
Asynchronous/Synchronous Clears | N/A | Output registers and output latches | Output registers and output latches |
Write/read operation triggering | Rising clock edges | Rising clock edges | Rising clock edges |
Same-port read-during-write | N/A | Output ports set to New Data or Don't Care | Output ports set to Don't Care |
Mixed-port read-during-write | Write-forwarding feature
|
|
Output ports set to New Data, Old Data, or Don't Care |
Error Correction Code (ECC) support |
|
|
Soft IP using the Quartus® Prime software |
Force-to-Zero | N/A | Supported | N/A |
Coherent read memory | N/A | Supported | N/A |
Freeze logic | N/A | Supported | N/A |
True dual port (TDP) dual clock emulator | N/A | Supported | N/A |