Intel® Stratix® 10 Power Management User Guide

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ID 683418
Date 10/31/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 Power Management Overview 2. Intel® Stratix® 10 Power Management Architecture and Features 3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide 4. Intel® Stratix® 10 Power Management User Guide Archives 5. Document Revision History for the Intel® Stratix® 10 Power Management User Guide
2. Intel® Stratix® 10 Power Management Architecture and Features x
2.1. Power Consumption 2.2. Power Reduction Techniques and Features 2.3. Power-On Reset Circuitry 2.4. Power Sequencing Considerations for Intel® Stratix® 10 Devices 2.5. Power Supply Design
2.1. Power Consumption x
2.1.1. Dynamic Power Equation
2.2. Power Reduction Techniques and Features x
2.2.1. SmartVID Standard Power Devices 2.2.2. Power-Screened Devices 2.2.3. Temperature Compensation 2.2.4. DSP and M20K Power Gating 2.2.5. Clock Gating 2.2.6. Power Sense Line
2.2.1. SmartVID Standard Power Devices x
2.2.1.1. SmartVID Feature Implementation in Intel® Stratix® 10 Devices 2.2.1.2. SDM Power Manager
2.2.1.2. SDM Power Manager x
2.2.1.2.1. PMBus Master Mode 2.2.1.2.2. PMBus Slave Mode
2.3. Power-On Reset Circuitry x
2.3.1. Power Supplies Monitored and Not Monitored by the POR Circuitry
2.4. Power Sequencing Considerations for Intel® Stratix® 10 Devices x
2.4.1. Power-Up Sequence Requirements for Intel® Stratix® 10 Devices 2.4.2. Power-Down Sequence Recommendations and Requirements for Intel® Stratix® 10 Devices
3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide x
3.1. Intel® Stratix® 10 Power Management and VID Interface Getting Started
3.1. Intel® Stratix® 10 Power Management and VID Interface Getting Started x
3.1.1. Specifying Parameters and Options
3.1.1. Specifying Parameters and Options x
3.1.1.1. Configuration Pin Parameters 3.1.1.2. Power Management and VID Parameters 3.1.1.3. Intel® Stratix® 10 Power Management and VID Interface QSF Constraint Guide
1. Intel® Stratix® 10 Power Management Overview
2. Intel® Stratix® 10 Power Management Architecture and Features
3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide
4. Intel® Stratix® 10 Power Management User Guide Archives
5. Document Revision History for the Intel® Stratix® 10 Power Management User Guide

2.4. Power Sequencing Considerations for Intel® Stratix® 10 Devices

The Intel® Stratix® 10 devices require a specific power-up and power-down sequence. This section describes several power management options and discusses proper I/O management during device power-up and power-down. Design your power supply solution to properly control the complete power sequence.

The requirements in this section must be followed to prevent unpredictable current draw to the FPGA device, which can potentially impact the I/O functionality. Intel® Stratix® 10 devices do not support 'Hot-Socketing' except under the conditions stated in the table below. The table below also shows what the unpowered pins can tolerate during power-up and power-down sequences.

The I/O pins are tri-stated with a weak pull-up during power up.

Table 8.  Pin Tolerance—Power-Up/Power-Down'√' is Applicable; '—' is Not Applicable.
Pin Type Power-Up Power-Down
Tristate Drive to GND Drive to VCCIO Driven with < 1.0 Vp-p Tristate Drive to GND Drive to VCCIO Driven with < 1.0 Vp-p
3VIO banks √ — — — √ √ — —
LVDS I/O banks √ √ √10 — √ √ √10 —
Differential Transceiver pins √ √ — √11 √ √ — √11

Section Content
Power-Up Sequence Requirements for Intel Stratix 10 Devices
Power-Down Sequence Recommendations and Requirements for Intel Stratix 10 Devices

Related Information
10 The maximum current allowed through any LVDS I/O bank pin when the device is unpowered or during power up/down conditions = 10 mA (refer to "LVDS I/O Pin Guidance for Unpowered FPGA Pins").
11 This applies to Intel® Stratix® 10 L-Tile/H-Tile only (refer to "Transceiver Pin Guidance for Unpowered FPGA Transceiver Pins").
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