Intel® Stratix® 10 Power Management User Guide

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ID 683418
Date 10/31/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 Power Management Overview 2. Intel® Stratix® 10 Power Management Architecture and Features 3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide 4. Intel® Stratix® 10 Power Management User Guide Archives 5. Document Revision History for the Intel® Stratix® 10 Power Management User Guide
2. Intel® Stratix® 10 Power Management Architecture and Features x
2.1. Power Consumption 2.2. Power Reduction Techniques and Features 2.3. Power-On Reset Circuitry 2.4. Power Sequencing Considerations for Intel® Stratix® 10 Devices 2.5. Power Supply Design
2.1. Power Consumption x
2.1.1. Dynamic Power Equation
2.2. Power Reduction Techniques and Features x
2.2.1. SmartVID Standard Power Devices 2.2.2. Power-Screened Devices 2.2.3. Temperature Compensation 2.2.4. DSP and M20K Power Gating 2.2.5. Clock Gating 2.2.6. Power Sense Line
2.2.1. SmartVID Standard Power Devices x
2.2.1.1. SmartVID Feature Implementation in Intel® Stratix® 10 Devices 2.2.1.2. SDM Power Manager
2.2.1.2. SDM Power Manager x
2.2.1.2.1. PMBus Master Mode 2.2.1.2.2. PMBus Slave Mode
2.3. Power-On Reset Circuitry x
2.3.1. Power Supplies Monitored and Not Monitored by the POR Circuitry
2.4. Power Sequencing Considerations for Intel® Stratix® 10 Devices x
2.4.1. Power-Up Sequence Requirements for Intel® Stratix® 10 Devices 2.4.2. Power-Down Sequence Recommendations and Requirements for Intel® Stratix® 10 Devices
3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide x
3.1. Intel® Stratix® 10 Power Management and VID Interface Getting Started
3.1. Intel® Stratix® 10 Power Management and VID Interface Getting Started x
3.1.1. Specifying Parameters and Options
3.1.1. Specifying Parameters and Options x
3.1.1.1. Configuration Pin Parameters 3.1.1.2. Power Management and VID Parameters 3.1.1.3. Intel® Stratix® 10 Power Management and VID Interface QSF Constraint Guide
1. Intel® Stratix® 10 Power Management Overview
2. Intel® Stratix® 10 Power Management Architecture and Features
3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide
4. Intel® Stratix® 10 Power Management User Guide Archives
5. Document Revision History for the Intel® Stratix® 10 Power Management User Guide

2.2.1.1. SmartVID Feature Implementation in Intel® Stratix® 10 Devices

Devices supporting the SmartVID feature have a VID-fused value programmed into a fuse block during device manufacturing. The VID-fused value represents a voltage level in the range of 0.8V to 0.94V. Each device has its own specific VID-fused value.

The VID-fused value is sent to the external regulator or system power controller through the PMBus interface. Upon receiving the VID-fused value, an adjustable regulator tunes the VCC and VCCP voltage levels to the voltage specified by the VID-fused value.

Intel® Stratix® 10 devices perform the SmartVID setup in the early stage of the configuration process. The SmartVID process will continue to monitor the VCC and VCCP voltage rails in user mode. The Power Manager monitors the temperature and adjusts the voltage when required. For more information, refer to the Temperature Compensation section.

Table 1.  SmartVID Regulator Requirements
Specification Value
Voltage range 0.8 V – 0.94 V
Voltage step 10 mV
Ramp time
  • Non-CvP—10 mV/10 ms to 10 mV/20 µs
  • Configuration via Protocol (CvP)—10 mV/60 µs to 10 mV/20 µs 1
Table 2.  Supported Voltage Output Format for Intel® Stratix® 10 Devices with the –V Power Option
Voltage Output Format Operating Modes
PMBus Master Mode PMBus Slave Mode
Linear mode Yes No
VID mode No No
Direct mode Yes Yes, with coefficient m=1, b=0, and R=0. Translated output voltage is in millivolts (mV).
Related Information
1 When the system is required to support the CvP functionality and meet the PCI Express* ( PCIe* ) link-up timing budget during the initial power up, the minimum ramp time is 10 mV/60 µs.
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