Stratix® 10 Power Management User Guide

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ID 683418
Date 10/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 Power Management Overview 2. Stratix® 10 Power Management Architecture and Features 3. Stratix® 10 Power Management and VID Interface Implementation Guide 4. Stratix® 10 Power Management User Guide Archives 5. Document Revision History for the Stratix® 10 Power Management User Guide
2. Stratix® 10 Power Management Architecture and Features x
2.1. Power Consumption 2.2. Power Reduction Techniques and Features 2.3. Power-On Reset Circuitry 2.4. Power Sequencing Considerations for Stratix® 10 Devices 2.5. Power Supply Design
2.1. Power Consumption x
2.1.1. Dynamic Power Equation
2.2. Power Reduction Techniques and Features x
2.2.1. SmartVID Standard Power Devices 2.2.2. Power-Screened Devices 2.2.3. Temperature Compensation 2.2.4. DSP and M20K Power Gating 2.2.5. Clock Gating 2.2.6. Power Sense Line
2.2.1. SmartVID Standard Power Devices x
2.2.1.1. SmartVID Feature Implementation in Stratix® 10 Devices 2.2.1.2. SDM Power Manager
2.2.1.2. SDM Power Manager x
2.2.1.2.1. PMBus Master Mode 2.2.1.2.2. PMBus Slave Mode
2.3. Power-On Reset Circuitry x
2.3.1. Power Supplies Monitored and Not Monitored by the POR Circuitry
2.4. Power Sequencing Considerations for Stratix® 10 Devices x
2.4.1. Power-Up Sequence Requirements for Stratix® 10 Devices 2.4.2. Power-Down Sequence Recommendations and Requirements for Stratix® 10 Devices Recommended Power-Down Ramp Specification Required Power-Down Ramp Specification Required Voltage Differential Specification Relaxed Power-Down Duration Specification
3. Stratix® 10 Power Management and VID Interface Implementation Guide x
3.1. Stratix® 10 Power Management and VID Interface Getting Started
3.1. Stratix® 10 Power Management and VID Interface Getting Started x
3.1.1. Specifying Parameters and Options
3.1.1. Specifying Parameters and Options x
3.1.1.1. Configuration Pin Parameters 3.1.1.2. Power Management and VID Parameters 3.1.1.3. Stratix® 10 Power Management and VID Interface QSF Constraint Guide
1. Stratix® 10 Power Management Overview
2. Stratix® 10 Power Management Architecture and Features
3. Stratix® 10 Power Management and VID Interface Implementation Guide
4. Stratix® 10 Power Management User Guide Archives
5. Document Revision History for the Stratix® 10 Power Management User Guide

2.4.2. Power-Down Sequence Recommendations and Requirements for Stratix® 10 Devices

Altera's FPGAs need to follow certain requirements during a power-down sequence. The power-down sequence can be a controlled power-down event via an on/off switch or an uncontrolled event as with a power supply collapse. In either case, you must follow a specific power-down sequence. Below are four power-down sequence specifications. They are either Recommended (one), Required (two), or Relaxed (one). To comply with Altera’s FPGA Power-Down requirements, the Recommended option is best.

Note: If you cannot follow the Recommended specification, you must follow the Required specification.

Recommended Power-Down Ramp Specification

This is the best option to minimize power supply currents.

Figure 11. Recommended Power-Down Ramp Specification
  • Power down all power rails fully within 100 ms.
  • Power down power supplies within the same Group in any order.
  • Before Group 3 supplies power down, power down all Group 4 supplies within 10% of GND.
  • Before Group 2 supplies power down, power down all Group 3 supplies within 10% of GND.
  • Before Group 1 supplies power down, power down all Group 2 supplies within 10% of GND.
  • The maximum voltage differential between any Group 3 supply and any Group 2 supply is 1.92 V, and only applicable for the 1.8V voltage rails in Group 2.
For Stratix® 10 GX and SX devices, you can combine and ramp down Group 3 power rails with Group 2 power rails if the two groups share the same voltage level and the same voltage regulator as the Group 2 power rails.
  • Ensure that the newly combined power rails do not cause any driving of unpowered GPIO or transceiver pins.
  • Ensure that the newly combined power rails do not violate any power-down sequencing specification due to device (third party) leakage; maintain the Required Voltage Differential Specification.

During the power-up/down sequence, the device output pins are tri-stated. To ensure long term reliability of the device, Altera recommends that you do not drive the input pins during this time.

Required Power-Down Ramp Specification

In cases where power supply is collapsing or if the recommended specification cannot be met, the following PDS sequence is required.

Figure 12. Required Power-Down Ramp Specification
  • Power down all power rails fully within 100 ms.
  • As soon as possible, disable all power supplies.
    • Tri-state Group 1 supplies, and do not drive them actively to GND.
    • If possible, drive or terminate Group 2, Group 3, and Group 4 supplies to GND.
  • Ensure no alternative sourcing of any power supply exists during the power-down sequence; reduce all supplies monotonically and with a consistent RC typical decay.
  • By the time any Group 1 supply goes under 0.35 V, all Group 2, Group 3, and Group 4 supplies must be under 1.0 V.

Required Voltage Differential Specification

To not excessively overstress device transistors during power-down, there is an additional voltage requirement between any two power supplies between different power groups during power-down:

ΔV < ΔVnom + 500 mV

Figure 13. Required Voltage Differential Specification
  • Power down all power rails fully within 100 ms.
  • For example, if Group 1 Voltage = 0.9 V, Group 2 Voltage = 1.8 V, and Group 3 Voltage = 3.0 V, then:

    G3Vnom = 3.0 V

    G2Vnom = 1.8 V

    G2Vnom = 1.8 V

    G1Vnom = 0.9 V

    G3Vnom = 3.0 V

    G1Vnom = 0.9 V

    (G3V – G2V)nom = 1.2 V (G2V – G1V)nom = 0.9 V (G3V – G1V)nom = 2.1 V
    (G3V – G2V) <= 1.2 V + .5 V (G2V – G1V) <= 0.9 V + .5 V (G3V – G1V) <= 2.1 V + .5 V
    (G3V – G2V) <= 1.7 V (G2V – G1V) <= 1.4 V (G3V – G1V) <= 2.6 V
  • To meet this voltage differential requirement, ramp down all power supplies as soon as possible according to the Required Power-Down Ramp Specification.
Note: Not following the required power sequence can result in unpredictable device operation and internal high current paths.

Relaxed Power-Down Duration Specification

For supplies being powered down with no active termination, voltage reduction to GND slows down as supply approaches 0 V. In this case, the 100 ms power requirement is relaxed - measure it when supply reaches near GND.

Figure 14. Relaxed Power-Down Duration Specification
  • Ensure all Group 1 supplies reach < 100 mV within 100 ms.
  • Ensure all Group 2, Group 3, and Group 4 supplies reach < 200 mV within 100 ms.
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