2.4.1. Power-Up Sequence Requirements for Intel® Stratix® 10 Devices

Intel® Stratix® 10 Power Management User Guide

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Date 10/31/2023

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2.4.1. Power-Up Sequence Requirements for Intel® Stratix® 10 Devices

Note: To satisfy the power-up requirements, program the FPGA device immediately after the power-up sequence completes.

The power rails in Intel® Stratix® 10 devices are each divided into three groups. Refer to the Intel® Stratix® 10 Device Family Pin Connection Guidelines and AN692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 Devices for additional details.

The diagram below illustrates the voltage groups of the Intel® Stratix® 10 devices and their required power-up sequence.

Figure 10. Power-Up Sequence for Intel® Stratix® 10 Devices

Note: VCCBAT is not in any of the groups below. VCCBAT does not have any sequence requirements. VCCBAT holds the contents of the security keys.

Table 9. Voltage Rails
Power Group	Intel® Stratix® 10 GX and SX (L-Tile and H-Tile)	Intel® Stratix® 10 MX (HBM, H-Tile, and E-Tile)	Intel® Stratix® 10 TX (H-Tile and E-Tile)	Intel® Stratix® 10 DX (E-Tile and P-Tile)
Group 1	V_CC V_CCP V_CCERAM V_{CCR_GXB} V_{CCT_GXB} V_{CCL_HPS} V_{CCPLLDIG_SDM} V_{CCPLLDIG_HPS}	V_CC V_CCP V_CCERAM V_{CCR_GXB} V_{CCT_GXB} V_{CCPLLDIG_SDM} V_{CCRT_GXE} V_{CCRTPLL_GXE}	V_CC V_CCP V_CCERAM V_{CCR_GXB} V_{CCT_GXB} V_{CCL_HPS} V_{CCPLLDIG_SDM} V_{CCPLLDIG_HPS} V_{CCRT_GXE} V_{CCRTPLL_GXE}	V_CC V_CCP V_CCERAM V_{CCFUSE_GXP} ¹² V_{CCRT_GXP} V_{CCL_HPS} V_{CCPLLDIG_SDM} V_{CCPLLDIG_HPS} V_{CCRT_GXE} V_{CCRTPLL_GXE}
Group 2	V_CCPT V_{CCH_GXB} V_{CCA_PLL} V_{CCPLL_HPS} V_{CCPLL_SDM} V_CCADC	V_CCPT V_{CCH_GXB} V_{CCA_PLL} V_{CCPLL_SDM} V_CCADC V_{CCM_WORD} ¹³ V_{CCH_GXE} V_{CCCLK_GXE}	V_CCPT V_{CCH_GXB} V_{CCA_PLL} V_{CCPLL_HPS} V_{CCPLL_SDM} V_CCADC V_{CCH_GXE} V_{CCCLK_GXE}	V_CCPT V_{CCA_PLL} V_{CCPLL_HPS} V_{CCPLL_SDM} V_CCADC V_{CCM_WORD} ¹³ V_{CCH_GXP} V_{CCCLK_GXP} V_{CCH_GXE} V_{CCCLK_GXE}
Group 3	V_CCIO ¹⁴ V_CCIO3V ¹⁴ V_{CCIO_SDM} ¹⁴ V_{CCIO_HPS} ¹⁴ V_{CCFUSEWR_SDM} V_CCIO3D ¹⁵	V_CCIO V_CCIO3V V_{CCIO_SDM} V_{CCIO_UIB} ¹³ V_{CCFUSEWR_SDM}	V_CCIO V_CCIO3V V_{CCIO_SDM} V_{CCIO_HPS} V_{CCFUSEWR_SDM}	V_CCIO V_{CCIO_SDM} V_{CCIO_HPS} V_{CCIO_UIB} ¹³ V_{CCFUSEWR_SDM}
Group 4	V_CCIO3C ¹⁵	—	—	—

All power rails in Group 1 must ramp up (in any order) to a minimum of 90% of their respective nominal voltage before the power rails from Group 2 can start ramping up.

The power rails within Group 2 can ramp up in any order after the last power rail in Group 1 ramps to the minimum threshold of 90% of its nominal voltage. All power rails in Group 2 must ramp to a minimum threshold of 90% of their nominal value before the Group 3 power rails can start ramping up.

The power rails within Group 3 can ramp up in any order after the last power rail in Group 2 ramps up to a minimum threshold of 90% of their full value.

Group 4 power rails can ramp up after the last power rail in Group 3 ramps up to a minimum threshold of 90% of their full value.

Note: E-tile devices must maintain the voltage rail groupings for the power-up sequencing as listed in the table above. V_{CCCLK_GXE} must be powered up before V_{CCIO_SDM}.

Note: For 1SG040 and 1SX040 devices, VCCIO_3D must be powered up before VCCIO_3C.

Note: Ensure that the newly combined power rails do not cause any driving of unpowered GPIO or transceiver pins.

All power rails must ramp up monotonically. The power-up sequence should meet either the standard or the fast POR delay time. The POR delay time depends on the POR delay setting you use. For the POR specifications of the Intel® Stratix® 10 devices, refer to the POR Specifications section in the Intel® Stratix® 10 Device Datasheet .

For configuration via protocol (CvP), the total t_RAMP must be less than 10 ms from the first power supply ramp-up to the last power supply ramp-up. Select a fast POR delay setting to allow sufficient time for the PCI Express* ( PCIe* ) link initialization and configuration. For more details about power supply ramp up for the CvP mode, refer to the Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide.

¹² You must always connect VCCFUSE_GXP to VCCERAM on your board.

¹³ Applies to Intel® Stratix® 10 MX and DX devices only.

¹⁴ For Intel® Stratix® 10 GX and SX devices, these power rails can be combined and shared using the same voltage regulator as the Group 2 power rail V_CCPT if all their voltages are 1.8V.

¹⁵ Applies to the 1SG040 and 1SX040 devices only.

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Intel® Stratix® 10 Power Management User Guide

2.4.1. Power-Up Sequence Requirements for Intel® Stratix® 10 Devices