Intel® Stratix® 10 Power Management User Guide

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ID 683418
Date 10/31/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 Power Management Overview 2. Intel® Stratix® 10 Power Management Architecture and Features 3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide 4. Intel® Stratix® 10 Power Management User Guide Archives 5. Document Revision History for the Intel® Stratix® 10 Power Management User Guide
2. Intel® Stratix® 10 Power Management Architecture and Features x
2.1. Power Consumption 2.2. Power Reduction Techniques and Features 2.3. Power-On Reset Circuitry 2.4. Power Sequencing Considerations for Intel® Stratix® 10 Devices 2.5. Power Supply Design
2.1. Power Consumption x
2.1.1. Dynamic Power Equation
2.2. Power Reduction Techniques and Features x
2.2.1. SmartVID Standard Power Devices 2.2.2. Power-Screened Devices 2.2.3. Temperature Compensation 2.2.4. DSP and M20K Power Gating 2.2.5. Clock Gating Root Clock Gate Sector Clock Gate I/O PLL Clock Gate 2.2.6. Power Sense Line
2.2.1. SmartVID Standard Power Devices x
2.2.1.1. SmartVID Feature Implementation in Intel® Stratix® 10 Devices 2.2.1.2. SDM Power Manager
2.2.1.2. SDM Power Manager x
2.2.1.2.1. PMBus Master Mode 2.2.1.2.2. PMBus Slave Mode
2.3. Power-On Reset Circuitry x
2.3.1. Power Supplies Monitored and Not Monitored by the POR Circuitry
2.4. Power Sequencing Considerations for Intel® Stratix® 10 Devices x
2.4.1. Power-Up Sequence Requirements for Intel® Stratix® 10 Devices 2.4.2. Power-Down Sequence Recommendations and Requirements for Intel® Stratix® 10 Devices
3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide x
3.1. Intel® Stratix® 10 Power Management and VID Interface Getting Started
3.1. Intel® Stratix® 10 Power Management and VID Interface Getting Started x
3.1.1. Specifying Parameters and Options
3.1.1. Specifying Parameters and Options x
3.1.1.1. Configuration Pin Parameters 3.1.1.2. Power Management and VID Parameters 3.1.1.3. Intel® Stratix® 10 Power Management and VID Interface QSF Constraint Guide
1. Intel® Stratix® 10 Power Management Overview
2. Intel® Stratix® 10 Power Management Architecture and Features
3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide
4. Intel® Stratix® 10 Power Management User Guide Archives
5. Document Revision History for the Intel® Stratix® 10 Power Management User Guide

2.2.5. Clock Gating

Clock gating can be used to reduce dynamic power consumption. When an application is idle, its clock can be gated temporarily and ungated based on wake-up events. This is done using user logic to enable or disable the global clock (GCLK) and sector clock (SCLK).

You can perform dynamic power reduction by gating the clock signals of any circuitry not used by the design in the Intel® Stratix® 10 devices.

Clock networks can be gated using one of the following methods:

Root Clock Gate

You can dynamically gate each clock network at the root level using the Clock Control Intel FPGA IP core.

Sector Clock Gate

You can dynamically gate each clock network at the clock sector level using the Clock Control Intel FPGA IP core.

I/O PLL Clock Gate

You can dynamically gate each output counter of the Intel® Stratix® 10 I/O PLL's using IOPLL reconfiguration.

Clock gating a large portion of your FPGA design could cause significant current change over a short time period when the gated circuitry is enabled or disabled. The maximum current step resulting from this clock gating should be sized such that it does not create noise exceeding the maximum allowed AC noise specification, as determined by the PDN decoupling design on your PCB. You can control the current step size by dividing a large gated area into smaller sub-regions and staging those regions to enter or exit power gating sequentially.

For more details, refer to the Clock Gating section in the Intel® Stratix® 10 Clocking and PLL User Guide.

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