Intel® Stratix® 10 Power Management User Guide

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ID 683418
Date 10/31/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 Power Management Overview 2. Intel® Stratix® 10 Power Management Architecture and Features 3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide 4. Intel® Stratix® 10 Power Management User Guide Archives 5. Document Revision History for the Intel® Stratix® 10 Power Management User Guide
2. Intel® Stratix® 10 Power Management Architecture and Features x
2.1. Power Consumption 2.2. Power Reduction Techniques and Features 2.3. Power-On Reset Circuitry 2.4. Power Sequencing Considerations for Intel® Stratix® 10 Devices 2.5. Power Supply Design
2.1. Power Consumption x
2.1.1. Dynamic Power Equation
2.2. Power Reduction Techniques and Features x
2.2.1. SmartVID Standard Power Devices 2.2.2. Power-Screened Devices 2.2.3. Temperature Compensation 2.2.4. DSP and M20K Power Gating 2.2.5. Clock Gating 2.2.6. Power Sense Line
2.2.1. SmartVID Standard Power Devices x
2.2.1.1. SmartVID Feature Implementation in Intel® Stratix® 10 Devices 2.2.1.2. SDM Power Manager
2.2.1.2. SDM Power Manager x
2.2.1.2.1. PMBus Master Mode 2.2.1.2.2. PMBus Slave Mode
2.3. Power-On Reset Circuitry x
2.3.1. Power Supplies Monitored and Not Monitored by the POR Circuitry
2.4. Power Sequencing Considerations for Intel® Stratix® 10 Devices x
2.4.1. Power-Up Sequence Requirements for Intel® Stratix® 10 Devices 2.4.2. Power-Down Sequence Recommendations and Requirements for Intel® Stratix® 10 Devices
3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide x
3.1. Intel® Stratix® 10 Power Management and VID Interface Getting Started
3.1. Intel® Stratix® 10 Power Management and VID Interface Getting Started x
3.1.1. Specifying Parameters and Options
3.1.1. Specifying Parameters and Options x
3.1.1.1. Configuration Pin Parameters 3.1.1.2. Power Management and VID Parameters 3.1.1.3. Intel® Stratix® 10 Power Management and VID Interface QSF Constraint Guide
1. Intel® Stratix® 10 Power Management Overview
2. Intel® Stratix® 10 Power Management Architecture and Features
3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide
4. Intel® Stratix® 10 Power Management User Guide Archives
5. Document Revision History for the Intel® Stratix® 10 Power Management User Guide

2.2.1. SmartVID Standard Power Devices

The SmartVID feature compensates for process variation by narrowing the process distribution using voltage adaptation. This feature is supported in devices with the –V standard power option only. For the –V standard power option devices, you must connect the PWRMGT_SCL and PWRMGT_SDA pins in both the Power Management BUS (PMBus™) master and PMBus slave modes. An additional PWRMGT_ALERT pin is required when you configure the Intel® Stratix® 10 device in the PMBus slave mode. All connections required must be set up on the circuit board and in the Intel® Quartus® Prime software.

For more information about how to connect these pins on the circuit board, refer to the Intel® Stratix® 10 Device Family Pin Connection Guidelines.

For instructions to set up the connection in the Intel® Quartus® Prime software, refer to the Specifying Parameters and Options.

Note: Intel® Stratix® 10 standard power devices (–1V, –2V, –3V power grade) are SmartVID devices. The core voltage supplies (VCC and VCCP) for each SmartVID device must be driven by a PMBus-compliant voltage regulator dedicated to the Intel® Stratix® 10 –V device that is connected to that Intel® Stratix® 10 device via PMBus. For Intel® Stratix® 10 standard power devices, use of a PMBus-compliant voltage regulator for each device is mandatory. Intel® Stratix® 10 devices will not configure or function correctly if the core voltage is driven by a non-PMBus compliant regulator with a fixed output voltage.

Intel programs the optimum voltage level required by each individual Intel® Stratix® 10 device into a fuse block during device manufacturing. The Secure Device Manager (SDM) Power Manager reads these values and can communicate them to an external power regulator or a system power controller through the PMBus interface.

The SmartVID feature allows a power regulator to provide the Intel® Stratix® 10 device with VCC and VCCP voltage levels that maintain the performance of the specific device speed grade. When the SmartVID feature is used:

  1. Intel® Stratix® 10 devices are initially powered up to a nominal voltage level of 0.9V for both VCC and VCCP .
  2. After the VID-fused value in the Intel® Stratix® 10 device is determined and propagated to the external voltage regulator, both the VCC and VCCP voltages are regulated based on the VID-fused value.

Section Content
SmartVID Feature Implementation in Intel Stratix 10 Devices
SDM Power Manager

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