AN 692: Power Sequencing Considerations for Cyclone® 10 GX, Arria® 10, Stratix® 10, Agilex™ 7, and Agilex™ 5 Devices

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ID 683725
Date 9/26/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview and Related Information
1. Overview and Related Information x
1.1. Controlled Sequence Designs 1.2. Fault Tolerance 1.3. Driving Unpowered FPGA Pins 1.4. Document Revision History for AN 692: Power Sequencing Considerations for Cyclone® 10 GX, Arria® 10, Stratix® 10, Agilex™ 7, and Agilex™ 5 Devices
1.1. Controlled Sequence Designs x
1.1.1. Programmable Power Management Controller (PPMC) 1.1.2. Low-Cost Discrete Sequencer Design
1.1.1. Programmable Power Management Controller (PPMC) x
1.1.1.1. PPMC Example Design 1.1.1.2. Multiple Supply Sequencer
1.1.2. Low-Cost Discrete Sequencer Design x
1.1.2.1. Low-Cost Sequencer Circuit Description 1.1.2.2. Low-Cost Discrete Sequencer Simulation Results
1.2. Fault Tolerance x
1.2.1. Managing Uncontrolled Loss of Power Events 1.2.2. Sequential vs. Simultaneous Power-Down 1.2.3. Voltage Regulators with Clamping Capability
1.3. Driving Unpowered FPGA Pins x
1.3.1. LVDS I/O Pin Guidance for Unpowered FPGA 1.3.2. Transceiver Pin Guidance for Unpowered FPGA 1.3.3. 3VIO Pin Guidance for Unpowered FPGA
1. Overview and Related Information

1.3.1. LVDS I/O Pin Guidance for Unpowered FPGA

The LVDS I/O pins do not support ‘Hot-Socketing;’ these LVDS I/O pins can tolerate a maximum of 10 mA per pin and a total of 100 mA per I/O bank. The voltage level of the LVDS I/O pin must not exceed 1.89 V.

A series resistor can be used to help limit current if necessary. The worst case assumption is that VCCIO is unpowered (0 V) while its LVDS I/O pin is driven with a voltage less than the allowable maximum (1.89 V). Refer to the figure below.

Figure 8. LVDS I/O Banks Buffer Structure
Level Two Title