Intel® Stratix® 10 Power Management User Guide

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ID 683418
Date 10/31/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 Power Management Overview 2. Intel® Stratix® 10 Power Management Architecture and Features 3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide 4. Intel® Stratix® 10 Power Management User Guide Archives 5. Document Revision History for the Intel® Stratix® 10 Power Management User Guide
2. Intel® Stratix® 10 Power Management Architecture and Features x
2.1. Power Consumption 2.2. Power Reduction Techniques and Features 2.3. Power-On Reset Circuitry 2.4. Power Sequencing Considerations for Intel® Stratix® 10 Devices 2.5. Power Supply Design
2.1. Power Consumption x
2.1.1. Dynamic Power Equation
2.2. Power Reduction Techniques and Features x
2.2.1. SmartVID Standard Power Devices 2.2.2. Power-Screened Devices 2.2.3. Temperature Compensation 2.2.4. DSP and M20K Power Gating 2.2.5. Clock Gating 2.2.6. Power Sense Line
2.2.1. SmartVID Standard Power Devices x
2.2.1.1. SmartVID Feature Implementation in Intel® Stratix® 10 Devices 2.2.1.2. SDM Power Manager
2.2.1.2. SDM Power Manager x
2.2.1.2.1. PMBus Master Mode 2.2.1.2.2. PMBus Slave Mode
2.3. Power-On Reset Circuitry x
2.3.1. Power Supplies Monitored and Not Monitored by the POR Circuitry
2.4. Power Sequencing Considerations for Intel® Stratix® 10 Devices x
2.4.1. Power-Up Sequence Requirements for Intel® Stratix® 10 Devices 2.4.2. Power-Down Sequence Recommendations and Requirements for Intel® Stratix® 10 Devices
3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide x
3.1. Intel® Stratix® 10 Power Management and VID Interface Getting Started
3.1. Intel® Stratix® 10 Power Management and VID Interface Getting Started x
3.1.1. Specifying Parameters and Options
3.1.1. Specifying Parameters and Options x
3.1.1.1. Configuration Pin Parameters 3.1.1.2. Power Management and VID Parameters 3.1.1.3. Intel® Stratix® 10 Power Management and VID Interface QSF Constraint Guide
1. Intel® Stratix® 10 Power Management Overview
2. Intel® Stratix® 10 Power Management Architecture and Features
3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide
4. Intel® Stratix® 10 Power Management User Guide Archives
5. Document Revision History for the Intel® Stratix® 10 Power Management User Guide

3.1.1.2. Power Management and VID Parameters

You can use the GUI parameters to configure the Power Management and VID interface if the VID operation is in the PMBus Master mode.

Table 11.  Power Management and VID Parameters
Parameters Value Description
Bus speed mode 16 100 KHz Bus speed mode of PMBus interface when operating in the PMBus Master mode.
400 KHz
Slave device type16 LTM4677

Supported device types.

Intel® recommends you to use one of the slave device type listed in the drop-down menu that has been tested with the Intel® FPGA tools. If you are not using one of the slave device type listed in the drop-down menu, select Other option. When you select Other option, refer to Table: SmartVID Regulator Requirements, Table: Supported Voltage Output Format for Intel® Stratix® 10 Devices with the –V Power Option, and Table: Supported Commands for the PMBus Master Mode for the voltage regulator requirements details.

Other
Device address in PMBus Slave mode17 7-bit hexadecimal value Device address in the PMBus Slave mode.
Slave device_0 address16 7-bit hexadecimal value

External power regulator address.

This parameter must be non-zero when you are using the PMBus Master mode.
Slave device_1 address16 7-bit hexadecimal value External power regulator address.
Slave device_2 address16 7-bit hexadecimal value External power regulator address.
Slave device_3 address16 7-bit hexadecimal value External power regulator address.
Slave device_4 address16 7-bit hexadecimal value External power regulator address.
Slave device_5 address16 7-bit hexadecimal value External power regulator address.
Slave device_6 address16 7-bit hexadecimal value External power regulator address.
Slave device_7 address16 7-bit hexadecimal value External power regulator address.
Voltage output format16 Auto discovery

The voltage output format when the operation mode is PMBus Master.

If the voltage output format is the Auto discovery or Direct format, you must set the following parameters:

  • Direct format coefficient m
  • Direct format coefficient b
  • Direct format coefficient R

If the voltage regulator is the Linear format, you must set the Linear format N parameter. 18

For all voltage output format, you must also select the correct "translated voltage output unit".
Direct format
Linear format
Direct format coefficient m16 Signed integer: -32768 to 32767 Direct format coefficient m of the slave device type when the operation mode is PMBus Master.
Direct format coefficient b16 Signed integer: -32768 to 32767 Direct format coefficient b of the slave device type when the operation mode is PMBus Master.
Direct format coefficient R16 Signed integer: -128 to 127 Direct format coefficient R of the slave device type when the operation mode is PMBus Master.
Linear format N16 –16 to 15 Output voltage command when the voltage output format is set to the Linear format.
Translated voltage value unit16 millivolts Indicates the translated output voltage is in millivolts (mV) or volts (V).
volts
Enable PAGE command16 Enable By enabling the PAGE command, the FPGA PMBus Master will use the PAGE command to set all the output channels (0xFF) on registered regulator modules to respond to VOUT_COMMAND. If only specified output channels on registered regulator modules must respond to VOUT_COMMAND, enter the corresponding page value (0x00 – 0xFF).
Disable
16 This parameter is used for the PMBus Master mode.
17 This parameter is used for the PMBus Slave mode.
18 N is the exponent of a 5-bit two's compliment integer.
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