Intel® Stratix® 10 Power Management User Guide

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ID 683418
Date 10/31/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 Power Management Overview 2. Intel® Stratix® 10 Power Management Architecture and Features 3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide 4. Intel® Stratix® 10 Power Management User Guide Archives 5. Document Revision History for the Intel® Stratix® 10 Power Management User Guide
2. Intel® Stratix® 10 Power Management Architecture and Features x
2.1. Power Consumption 2.2. Power Reduction Techniques and Features 2.3. Power-On Reset Circuitry 2.4. Power Sequencing Considerations for Intel® Stratix® 10 Devices 2.5. Power Supply Design
2.1. Power Consumption x
2.1.1. Dynamic Power Equation
2.2. Power Reduction Techniques and Features x
2.2.1. SmartVID Standard Power Devices 2.2.2. Power-Screened Devices 2.2.3. Temperature Compensation 2.2.4. DSP and M20K Power Gating 2.2.5. Clock Gating 2.2.6. Power Sense Line
2.2.1. SmartVID Standard Power Devices x
2.2.1.1. SmartVID Feature Implementation in Intel® Stratix® 10 Devices 2.2.1.2. SDM Power Manager
2.2.1.2. SDM Power Manager x
2.2.1.2.1. PMBus Master Mode 2.2.1.2.2. PMBus Slave Mode
2.3. Power-On Reset Circuitry x
2.3.1. Power Supplies Monitored and Not Monitored by the POR Circuitry
2.4. Power Sequencing Considerations for Intel® Stratix® 10 Devices x
2.4.1. Power-Up Sequence Requirements for Intel® Stratix® 10 Devices 2.4.2. Power-Down Sequence Recommendations and Requirements for Intel® Stratix® 10 Devices
3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide x
3.1. Intel® Stratix® 10 Power Management and VID Interface Getting Started
3.1. Intel® Stratix® 10 Power Management and VID Interface Getting Started x
3.1.1. Specifying Parameters and Options
3.1.1. Specifying Parameters and Options x
3.1.1.1. Configuration Pin Parameters 3.1.1.2. Power Management and VID Parameters 3.1.1.3. Intel® Stratix® 10 Power Management and VID Interface QSF Constraint Guide
1. Intel® Stratix® 10 Power Management Overview
2. Intel® Stratix® 10 Power Management Architecture and Features
3. Intel® Stratix® 10 Power Management and VID Interface Implementation Guide
4. Intel® Stratix® 10 Power Management User Guide Archives
5. Document Revision History for the Intel® Stratix® 10 Power Management User Guide

3.1.1. Specifying Parameters and Options

Follow these steps to specify the Power Management and VID parameters and options.

  1. Create an Intel® Quartus® Prime project using the New Project Wizard available from the File menu.
  2. On the Assignments menu, click Device.
  3. On the Device dialog box, click Device and Pin Options.
  4. On the Device and Pin Options dialog box, click Configuration.
  5. On the Configuration page, specify the VID Operation mode. There are two modes available—PMBus Master and PMBus Slave.
  6. Both the PMBus Master and PMBus Slave modes require the PWMGT_SDA and PWMGT_SCL pins. For the PMBus Slave mode, additional PWRMGT_ALERT pin is required. To configure these pins, on the Configuration page, click Configuration Pin Options. For the configuration pin parameters, refer to Table: Configuration Pin Parameters.
  7. On the Configuration Pin dialog box, assign the appropriate SDM_IO pin to the power management pins. Click OK.
  8. On the Device and Pin Options dialog box, click Power Management and VID to specify the device settings if your device is in the PMBus Master mode. Click OK. For the power management and VID parameters, refer to Table: Power Management and VID Parameters.

This completes the SmartVID setup for the Intel® Stratix® 10 device.


Section Content
Configuration Pin Parameters
Power Management and VID Parameters
Intel Stratix 10 Power Management and VID Interface QSF Constraint Guide

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