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1.1. Instantiating the Partial Reconfiguration IP Core in the Qsys Interface
1.2. Instantiating the Partial Reconfiguration IP Core in the Intel® Quartus® Prime IP Catalog
1.3. Enable Compression
1.4. Enable Enhanced Decompression
1.5. Data Compression Comparison
1.6. Bitstream Compatibility Check
1.7. Clock-to-Data Ratio (CD Ratio)
1.8. Partial Reconfiguration IP Core Parameters
1.9. Partial Reconfiguration IP Core Ports
1.10. Reconfiguration Sequence
1.11. Slave Interface
1.12. FPGA Control Block Interface
1.13. Freeze Logic for 28-nm PR Regions
1.14. Data Source Controller
1.15. Standard Partial Reconfiguration Data Interface
1.16. JTAG Debug Mode for Partial Reconfiguration
1.17. Partial Reconfiguration IP Core User Guide Archives
1.18. Revision History
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1.15. Standard Partial Reconfiguration Data Interface
The PR data interface provides you with selectable input data width; x1, x8, x16, and x32. The data interface is connected to ASMI_PARALLEL as well as the Avalon interface to obtain PR data from on-chip RAM, external flash device, or PR over PCIe.
For Cyclone® V and Stratix® V devices, if the input data width is other than x16, the PR IP core includes a data upsize or downsize module so that the data output to the Data Source Controller is always x16.