Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration Intel® FPGA IP

ID 683404
Date 4/18/2019
Public

1.12. FPGA Control Block Interface

When you instantiate the PR IP core, you can choose to use it as either an internal host or external host.
  • When you use the PR IP core as an internal host, it automatically instantiates the corresponding device CRCBLOCK and PRBLOCK WYSIWYG atom primitives.
  • When you use the PR IP core as external host (placed in another FPGA or CPLD), the PR IP core provides the CRCBLOCK and PRBLOCK interface ports so you can connect the host to the dedicated PR pins and CRC_ERROR pin on the target FPGA being partially reconfigured.