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1.1. Instantiating the Partial Reconfiguration IP Core in the Qsys Interface
1.2. Instantiating the Partial Reconfiguration IP Core in the Intel® Quartus® Prime IP Catalog
1.3. Enable Compression
1.4. Enable Enhanced Decompression
1.5. Data Compression Comparison
1.6. Bitstream Compatibility Check
1.7. Clock-to-Data Ratio (CD Ratio)
1.8. Partial Reconfiguration IP Core Parameters
1.9. Partial Reconfiguration IP Core Ports
1.10. Reconfiguration Sequence
1.11. Slave Interface
1.12. FPGA Control Block Interface
1.13. Freeze Logic for 28-nm PR Regions
1.14. Data Source Controller
1.15. Standard Partial Reconfiguration Data Interface
1.16. JTAG Debug Mode for Partial Reconfiguration
1.17. Partial Reconfiguration IP Core User Guide Archives
1.18. Revision History
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1.12. FPGA Control Block Interface
When you instantiate the PR IP core, you can choose to use it as either an internal host or external host.
- When you use the PR IP core as an internal host, it automatically instantiates the corresponding device CRCBLOCK and PRBLOCK WYSIWYG atom primitives.
- When you use the PR IP core as external host (placed in another FPGA or CPLD), the PR IP core provides the CRCBLOCK and PRBLOCK interface ports so you can connect the host to the dedicated PR pins and CRC_ERROR pin on the target FPGA being partially reconfigured.