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1.1. Instantiating the Partial Reconfiguration IP Core in the Qsys Interface
1.2. Instantiating the Partial Reconfiguration IP Core in the Intel® Quartus® Prime IP Catalog
1.3. Enable Compression
1.4. Enable Enhanced Decompression
1.5. Data Compression Comparison
1.6. Bitstream Compatibility Check
1.7. Clock-to-Data Ratio (CD Ratio)
1.8. Partial Reconfiguration IP Core Parameters
1.9. Partial Reconfiguration IP Core Ports
1.10. Reconfiguration Sequence
1.11. Slave Interface
1.12. FPGA Control Block Interface
1.13. Freeze Logic for 28-nm PR Regions
1.14. Data Source Controller
1.15. Standard Partial Reconfiguration Data Interface
1.16. JTAG Debug Mode for Partial Reconfiguration
1.17. Partial Reconfiguration IP Core User Guide Archives
1.18. Revision History
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1.5. Data Compression Comparison
Standard compression results in a 30-45% decrease in .rbf size. Use of the enhanced data compression algorithm results in 55-75% decrease in .rbf size. The algorithm increases the compression at the expense of additional core area required to implement the compression algorithm.
The following figure shows the compression ratio comparison across PR designs with varying degrees of Logic Element (LE):
Figure 5. Compression Ratio Comparison between Standard Compression and Enhanced Compression