Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration Intel® FPGA IP

ID 683404
Date 4/18/2019
Public

1.18. Revision History

Date Version Changes
April 2019 2019.04.18
  • Fixed typos.
  • Fixed two broken links.
  • Added taxonomy terms.
  • Altered the document title.
May 2017 2017.05.08

Removed support for Intel® Arria® 10 devices. For Intel® Arria® 10 support refer to the Partial Reconfiguration Solutions IP User Guide

Oct 2016 2016.10.31

Added support for Intel® Arria® 10 devices.

  • Updated content for Clock-to-Data Ratio.
  • Updated the Parameters and Ports.
  • Updated Compression instructions for standard and enhanced compression.
  • Added supporting content on using PR with JTAG.
  • Minor edits and fixed typos

May 2016 2016.05.02 Minor changes:
  • Fixed a link to the Designing for Partial Reconfiguration chapter in Vol 1 of the Intel® Quartus® Prime Handbook.
  • Fixed typos.
Nov 2015 2015.11.20 Revised the following topics:
  • Partial Reconfiguration IP Core Parameters—updated supported data width
  • Partial Reconfiguration IP Core Timing Specification—revised the timing diagram
  • Deprecated the Sample Partial Reconfiguration IP Core as an External Host on the Same Device topic
  • Added Enable Enhanced Compression topic
May 2015 2015.05.04 Revised the following topics:
  • Partial Reconfiguration IP Core Parameters—added new parameters for device family support
  • Partial Reconfiguration IP Core Ports—added new port options
  • Partial Reconfiguration IP Core Timing Specification—revised the timing diagram
January 2015 2015.01.29 Minor error corrections.
August 2014 2014.08.20
  • Added Avalon Memory Map slave interface

  • Updated Ports and Parameters to support Avalon Memory Map slave interface

  • Added Bitstream compatibility checking

  • Added sample pseudo-code for creating a freeze wrapper for multiple PR regions and creating an external host on the same device.

November 2013 2013.11.04 Initial release