Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration Intel® FPGA IP

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ID 683404
Date 4/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Partial Reconfiguration IP Core
1. Partial Reconfiguration IP Core x
1.1. Instantiating the Partial Reconfiguration IP Core in the Qsys Interface 1.2. Instantiating the Partial Reconfiguration IP Core in the Intel® Quartus® Prime IP Catalog 1.3. Enable Compression 1.4. Enable Enhanced Decompression 1.5. Data Compression Comparison 1.6. Bitstream Compatibility Check 1.7. Clock-to-Data Ratio (CD Ratio) 1.8. Partial Reconfiguration IP Core Parameters 1.9. Partial Reconfiguration IP Core Ports 1.10. Reconfiguration Sequence 1.11. Slave Interface 1.12. FPGA Control Block Interface 1.13. Freeze Logic for 28-nm PR Regions 1.14. Data Source Controller 1.15. Standard Partial Reconfiguration Data Interface 1.16. JTAG Debug Mode for Partial Reconfiguration 1.17. Partial Reconfiguration IP Core User Guide Archives 1.18. Revision History
1.3. Enable Compression x
1.3.1. PR Bitstream Compression and Encryption ( Intel® Arria® 10 Designs) 1.3.2. Generating an Encrypted PR Bitstream
1.11. Slave Interface x
1.11.1. Interrupt Interface
1.12. FPGA Control Block Interface x
1.12.1. Partial Reconfiguration IP Core Timing Specification 1.12.2. Avalon® -MM Slave Interface Read and Write Transfer Timing
1.16. JTAG Debug Mode for Partial Reconfiguration x
1.16.1. Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode
1. Partial Reconfiguration IP Core

1.9. Partial Reconfiguration IP Core Ports

I/O Port List for PR IP Core

Table 3.  Clock/Reset Ports
Port Name Width Direction Function

nreset

1

Input

Asynchronous reset for the PR IP core. Resetting the PR IP core during a partial reconfiguration operation can cause the device to lock up.

clk

1

Input

User input clock to the PR IP core.

This signal is ignored during JTAG debug operations. The input clock must be free-running.

Note: These options are always available.
Table 4.  Conduit Interface
Port Name Width Direction Function

freeze

1

Output

Active high signal used to freeze the PR interface signals of the region undergoing partial reconfiguration. De-assertion of this signal indicates the end of PR operation.

Note: Input freeze is required for Cyclone® V and Stratix® V devices. Refer to the Freeze Logic for PR Regions topic for more information.
Note: This option is always available.
Table 5.  Conduit Interface
Port Name Width Direction Function

pr_start

1

Input

A signal arriving at this port asserted high initiates a PR event. You must assert this signal high for a minimum of one clock cycle and de-assert it low prior to the end of the PR operation. This makes the PR IP core ready to accept the next pr_start trigger event when the freeze signal is low.

The PR IP core ignores this signal during JTAG debug operations.

data[]

1, 8, 16, or 32

Input

Selectable input PR data bus width, either x1, x8, x16, or x32.

Once a PR event is triggered, it is synchronous with the rising edge of the clk signal whenever the data_valid signal is high and the data_ready signal is high.

The PR IP core ignores this signal during JTAG debug operations.

data_valid

1

Input

A signal arriving at this port asserted high indicates the data[] port contains valid data.

The PR IP core ignores this signal during JTAG debug operations.

data_ready

1

Output

A signal arriving at this port asserted high indicates the PR IP core is ready to read the valid data on the data[] port whenever the data_valid signal is asserted high. The data sender must stop sending valid data if this port is low.

This signal deasserts low during JTAG debug operations.

status[2..0]

1

Output

A 3-bit error output used to indicate the status of PR event. Once an error is detected (PR_ERROR, CRC_ERROR, or incompatible bitstream error), this signal latches high and only resets at the beginning of the next PR event, when pr_start is high and freeze is low. For example:

3’b000 – power-up or nreset asserted

3’b001 – PR_ERROR was triggered

3’b010 – CRC_ERROR was triggered

3’b011 – Incompatible bitstream error detected

3’b100 – PR operation in progress

3’b101 – PR operation passed

3'b110 – Reserved

3'b111 – Reserved

double_pr

1

Input

When the pr_start signal is triggered, until the de-assertion of a freeze signal, a signal asserted high on this port indicates the PR event requires double PR cycle. A low signal on this port indicates a single PR cycle event.

If your PR design targets a Stratix® V device and requires the use of double PR because you have initialized RAM in the PR region, you must assert the double_pr input signal high. This assertion ensures that the controller handles double PR properly. If you are instantiating the PR IP in a design that is not using initialized on-chip RAMs, connect this port to 0.

You must assert this signal high if the PR bitstream (.rbf) is generated with the Write memory contents option turned on. Failure to do so causes a PR_ERROR assertion during partial reconfiguration.

The PR IP core ignores this signal during JTAG debug operations.

Note: These options are available when Enable Avalon-MM slave interface parameter is turned Off.
Table 6.  Avalon-MM Slave Interface
Port Name Width Direction Function

avmm_slave_address

1

Input

Avalon-MM address bus. The address bus is in the unit of Word addressing.

Refer to the Qsys Component section for more details on the address mapping.

The PR IP core ignores this signal during JTAG debug operations.

avmm_slave_read 1

Input

Avalon-MM read control.

The PR IP core ignores this signal during JTAG debug operations.

avmm_slave_readdata 16 or 32

Output

Avalon-MM read data bus.

The PR IP core ignores this signal during JTAG debug operations.

avmm_slave_write 1

Input

Avalon-MM write control.

The PR IP core ignores this signal during JTAG debug operations.

avmm_slave_writedata 16 or 32

Input

Avalon-MM write data bus.

The PR IP core ignores this signal during JTAG debug operations.

avmm_slave_waitrequest 1

Output

Asserted to indicate that the IP is busy. Also indicates that the IP core is unable to respond to a read or write request.

This signal is pulled high during JTAG debug operations.
Note: These options are available when Enable Avalon-MM Slave Interface parameter is turned On.
Table 7.  Interrupt Interface
Port Name Width Direction Function

irq

1

Output

The interrupt signal.
Note: This option is available when Enable interrupt interface parameter is turned On.
Table 8.  CRCBLOCK Interface These options are available when Use as PR Internal Host parameter is turned Off or the CRCBLOCK is instantiated manually for an internal host.
Port Name Width Direction Function

crc_error_pin

1

Input

Available when you use the PR IP core as an External Host. Connect this port to the dedicated CRC_ERROR pin of the FPGA undergoing partial reconfiguration.

Table 9.   PR Block Interface
Port Name Width Direction Function

pr_ready_pin

1

Input

Connect this port to the dedicated PR_READY pin of the FPGA undergoing partial reconfiguration.

pr_error_pin

1

Input

Connect this port to the dedicated PR_ERROR pin of the FPGA undergoing partial reconfiguration.

pr_done_pin

1

Input

Connect this port to the dedicated PR_DONE pin of the FPGA undergoing partial reconfiguration.

pr_request_pin

1

Output

Connect this port to the dedicated PR_REQUEST pin of the FPGA undergoing partial reconfiguration.

pr_clk_pin

1

Output

Connect this port to the dedicated DCLK of the FPGA undergoing partial reconfiguration.

pr_data_pin[15..0]

16

Output

Connect this port to the dedicated DATA[15..0] pins of the FPGA undergoing partial reconfiguration.

Note: These options are available when Use as PR Internal Host parameter is turned Off or when the PRBLOCK is instantiated manually for an internal host.
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