Intel® Acceleration Stack User Guide: Intel® FPGA Programmable Acceleration Card N3000-N/2

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ID 683362
Date 11/01/2021
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. System Requirements 3. Hardware Installation 4. Installing the OPAE Software 5. Identify the Intel® MAX® 10 BMC Version 6. Intel XL710 Driver Installation and Firmware Update 7. Updating the Retimer Firmware 8. OPAE Tools 9. Sample Test: Native Loopback 10. Configuring Ethernet Interfaces 11. Testing Network Loopback Using Data Plane Development Kit (DPDK) 12. Graceful Shutdown 13. Single Event Upset (SEU) 14. Document Revision History for Intel Acceleration Stack User Guide: Intel® FPGA PAC N3000-N/2 A. Troubleshooting B. fpgabist Sample Output
1. About this Document x
1.1. Acronym List
3. Hardware Installation x
3.1. Installing the Intel® FPGA PAC N3000-N/2
4. Installing the OPAE Software x
4.1. Install the Release Package
4.1. Install the Release Package x
4.1.1. Remove Previous OPAE Packages 4.1.2. Install the Acceleration Stack for Runtime 4.1.3. Install the Acceleration Stack for Development 4.1.4. Verify the OPAE Installation
4.1.2. Install the Acceleration Stack for Runtime x
4.1.2.1. For RHEL 4.1.2.2. For CentOS
4.1.2.2. For CentOS x
4.1.2.2.1. Download kernel 4.19 4.1.2.2.2. Build and Install kernel 4.19 4.1.2.2.3. Install OPAE in kernel 4.19
5. Identify the Intel® MAX® 10 BMC Version x
5.1. FPGA Factory Image Overview
6. Intel XL710 Driver Installation and Firmware Update x
6.1. Installing the Intel XL710 Driver 6.2. Updating the Intel XL710 Firmware
8. OPAE Tools x
8.1. Using fpgasupdate 8.2. Using fpgainfo 8.3. Test PCIe and External Memories with fpgabist 8.4. Test Network Loopback using fpgadiag
10. Configuring Ethernet Interfaces x
10.1. Modifying the Interface Maximum Transmission Unit (MTU) Size 10.2. Setting Forward Error Correction (FEC) Mode 10.3. Ethernet Pause Flow Control 10.4. Get Link Statistics 10.5. Ethernet Link Status
11. Testing Network Loopback Using Data Plane Development Kit (DPDK) x
11.1. Test Using an External Traffic Generator 11.2. Revert Back from DPDK to OPAE
12. Graceful Shutdown x
12.1. Using OPAE
13. Single Event Upset (SEU) x
13.1. OPAE Handling of SEU
A. Troubleshooting x
A.1. If OPAE installation verification fails, how to install OPAE manually?
B. fpgabist Sample Output x
B.1. For 4x25G Configuration B.2. For 2x2x25G Configuration
1. About this Document
2. System Requirements
3. Hardware Installation
4. Installing the OPAE Software
5. Identify the Intel® MAX® 10 BMC Version
6. Intel XL710 Driver Installation and Firmware Update
7. Updating the Retimer Firmware
8. OPAE Tools
9. Sample Test: Native Loopback
10. Configuring Ethernet Interfaces
11. Testing Network Loopback Using Data Plane Development Kit (DPDK)
12. Graceful Shutdown
13. Single Event Upset (SEU)
14. Document Revision History for Intel Acceleration Stack User Guide: Intel® FPGA PAC N3000-N/2
A. Troubleshooting
B. fpgabist Sample Output

10.3. Ethernet Pause Flow Control

The Intel® FPGA PAC N3000-N/2 supports pause frame operation for:
  • 25G as described in Flow Control section of 25G Ethernet Intel Arria 10 FPGA IP User Guide.
The Intel provided FPGA image supports generation of pause frames in response to the internal Intel® Arria® 10 buffer nearing an overflow condition. The provided FPGA image does not support response to received pause frames. The pause frame generation and response to pause frame reception is disabled by default. You can read the current setting of pause frame generation using: 
$ ethtool --show-pause npacf0g0l0

Pause parameters for npacf0g0l0:
Autonegotiate:	off
RX:		off
TX:		off
To turn on the pause frame generation:
  1. If you have more than one Intel® FPGA PAC N3000-N/2 installed in your server, first determine the proper sysfs entry for setting the transmit pause registers.
  2. Set Transmit Pause Quanta: Configurable register used to set the desired delay time embedded in the pause frame packet requesting peer to stop transmitting for a period defined in the quanta. One quanta equals 512-bit times.
  3. Set Transmit Hold-off Quanta: Configurable register used to set the desired delay time between consecutive pause frames packets in quanta.
  4. Pause Frame Enable: Allows you to enable or disable pause frame behavior using the ethtool.
Each Ethernet port has a set of transmit pause or hold-off registers. To find the proper sysfs entry, use the following command: 
$ ls -l /sys/class/fpga/intel-fpga-dev.*
Sample output: 
lrwxrwxrwx. 1 root root 0 Apr  1 06:13 /sys/class/fpga/intel-fpga-dev.0 -> ../../devices/pci0000:85/0000:85:00.0/0000:86:00.0/0000:87:09.0/0000:8a:00.0/fpga/intel-fpga-dev.0

lrwxrwxrwx. 1 root root 0 Apr  1 09:01 /sys/class/fpga/intel-fpga-dev.1 -> ../../devices/pci0000:17/0000:17:00.0/0000:18:00.0/0000:19:09.0/0000:1b:00.0/fpga/intel-fpga-dev.1
In the output above, there are two Intel® FPGA PAC N3000-N/2. For this example, the PCIe device ID of the desired card is 1b:00.0, hence the base sysfs path is /sys/class/fpga/intel-fpga-dev.1.
Setting the Transmit Pause Quanta sysfs entry to 200 quanta for port 0: 
# echo 200 > /sys/class/fpga/intel-fpga-dev.1/intel-fpga-fme.1/pac_n3000_net.10.auto/net/npacf1g0l0/tx_pause_frame_quanta

# cat /sys/class/fpga/intel-fpga-dev.1/intel-fpga-fme.1/pac_n3000_net.10.auto/net/npacf1g0l0/tx_pause_frame_quanta 

0xc8
Setting the Transmit Hold-off Quanta sysfs entry to 200 quanta for port 0: 
# echo 200 > /sys/class/fpga/intel-fpga-dev.1/intel-fpga-fme.1/pac_n3000_net.10.auto/net/npacf1g0l0/tx_pause_frame_holdoff

# cat /sys/class/fpga/intel-fpga-dev.1/intel-fpga-fme.1/pac_n3000_net.10.auto/net/npacf1g0l0/tx_pause_frame_holdoff

0xc8
To verify: 
# ethtool --pause npacf0g0l0 tx on

# ethtool --show-pause npacf0g0l0

Pause parameters for npacf0g0l0:
Autonegotiate:	off
RX:		off
TX:		on
Note: All Ethernet settings listed in this section are not persistent across power cycles or server reboots or rsu. After power cycle or server reboot or rsu, the Intel® FPGA PAC N3000-N/2 returns to default settings. The rsu command causes change in the PCIe B:D.F value.
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