Intel® Acceleration Stack User Guide: Intel® FPGA Programmable Acceleration Card N3000-N/2

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ID 683362
Date 11/01/2021
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. System Requirements 3. Hardware Installation 4. Installing the OPAE Software 5. Identify the Intel® MAX® 10 BMC Version 6. Intel XL710 Driver Installation and Firmware Update 7. Updating the Retimer Firmware 8. OPAE Tools 9. Sample Test: Native Loopback 10. Configuring Ethernet Interfaces 11. Testing Network Loopback Using Data Plane Development Kit (DPDK) 12. Graceful Shutdown 13. Single Event Upset (SEU) 14. Document Revision History for Intel Acceleration Stack User Guide: Intel® FPGA PAC N3000-N/2 A. Troubleshooting B. fpgabist Sample Output
1. About this Document x
1.1. Acronym List
3. Hardware Installation x
3.1. Installing the Intel® FPGA PAC N3000-N/2
4. Installing the OPAE Software x
4.1. Install the Release Package
4.1. Install the Release Package x
4.1.1. Remove Previous OPAE Packages 4.1.2. Install the Acceleration Stack for Runtime 4.1.3. Install the Acceleration Stack for Development 4.1.4. Verify the OPAE Installation
4.1.2. Install the Acceleration Stack for Runtime x
4.1.2.1. For RHEL 4.1.2.2. For CentOS
4.1.2.2. For CentOS x
4.1.2.2.1. Download kernel 4.19 4.1.2.2.2. Build and Install kernel 4.19 4.1.2.2.3. Install OPAE in kernel 4.19
5. Identify the Intel® MAX® 10 BMC Version x
5.1. FPGA Factory Image Overview
6. Intel XL710 Driver Installation and Firmware Update x
6.1. Installing the Intel XL710 Driver 6.2. Updating the Intel XL710 Firmware
8. OPAE Tools x
8.1. Using fpgasupdate 8.2. Using fpgainfo 8.3. Test PCIe and External Memories with fpgabist 8.4. Test Network Loopback using fpgadiag
10. Configuring Ethernet Interfaces x
10.1. Modifying the Interface Maximum Transmission Unit (MTU) Size 10.2. Setting Forward Error Correction (FEC) Mode 10.3. Ethernet Pause Flow Control 10.4. Get Link Statistics 10.5. Ethernet Link Status
11. Testing Network Loopback Using Data Plane Development Kit (DPDK) x
11.1. Test Using an External Traffic Generator 11.2. Revert Back from DPDK to OPAE
12. Graceful Shutdown x
12.1. Using OPAE
13. Single Event Upset (SEU) x
13.1. OPAE Handling of SEU
A. Troubleshooting x
A.1. If OPAE installation verification fails, how to install OPAE manually?
B. fpgabist Sample Output x
B.1. For 4x25G Configuration B.2. For 2x2x25G Configuration
1. About this Document
2. System Requirements
3. Hardware Installation
4. Installing the OPAE Software
5. Identify the Intel® MAX® 10 BMC Version
6. Intel XL710 Driver Installation and Firmware Update
7. Updating the Retimer Firmware
8. OPAE Tools
9. Sample Test: Native Loopback
10. Configuring Ethernet Interfaces
11. Testing Network Loopback Using Data Plane Development Kit (DPDK)
12. Graceful Shutdown
13. Single Event Upset (SEU)
14. Document Revision History for Intel Acceleration Stack User Guide: Intel® FPGA PAC N3000-N/2
A. Troubleshooting
B. fpgabist Sample Output

1.1. Acronym List

Acronym Expansion Description
Intel® FPGA PAC Intel FPGA Programmable Acceleration Card Intel® FPGA PAC N3000-N/2 is a full-duplex 100 Gbps in-system re-programmable acceleration card for multi-workload networking application acceleration.
AFU Accelerator Functional Unit Hardware Accelerator implemented in FPGA logic which offloads a computational operation for an application from the CPU to improve performance.
AF Acceleration Function Compiled Hardware Accelerator image implemented in FPGA logic that accelerates an application.
API Application Programming Interface A set of subroutine definitions, protocols, and tools for building software applications.
FIU FPGA Interface Unit FIU is a platform interface layer that acts as a bridge between platform interfaces like PCIe* and AFU-side interfaces such as CCI-P.
OPAE Open Programmable Acceleration Engine The OPAE is a set of drivers, utilities, and API's for managing and accessing AFs.
FME FPGA Management Engine The FME provides information about the FPGA platform including the OPAE version.
RSU Remote System Update

An RSU operation sends an instruction to the device to trigger a power cycle of the Intel® FPGA PAC N3000-N/2 only. This will force reconfiguration from flash for either Intel® MAX® 10 BMC image (on devices that support it) or the FPGA image.

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