Intel® Acceleration Stack User Guide: Intel® FPGA Programmable Acceleration Card N3000-N/2

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ID 683362
Date 11/01/2021
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. System Requirements 3. Hardware Installation 4. Installing the OPAE Software 5. Identify the Intel® MAX® 10 BMC Version 6. Intel XL710 Driver Installation and Firmware Update 7. Updating the Retimer Firmware 8. OPAE Tools 9. Sample Test: Native Loopback 10. Configuring Ethernet Interfaces 11. Testing Network Loopback Using Data Plane Development Kit (DPDK) 12. Graceful Shutdown 13. Single Event Upset (SEU) 14. Document Revision History for Intel Acceleration Stack User Guide: Intel® FPGA PAC N3000-N/2 A. Troubleshooting B. fpgabist Sample Output
1. About this Document x
1.1. Acronym List
3. Hardware Installation x
3.1. Installing the Intel® FPGA PAC N3000-N/2
4. Installing the OPAE Software x
4.1. Install the Release Package
4.1. Install the Release Package x
4.1.1. Remove Previous OPAE Packages 4.1.2. Install the Acceleration Stack for Runtime 4.1.3. Install the Acceleration Stack for Development 4.1.4. Verify the OPAE Installation
4.1.2. Install the Acceleration Stack for Runtime x
4.1.2.1. For RHEL 4.1.2.2. For CentOS
4.1.2.2. For CentOS x
4.1.2.2.1. Download kernel 4.19 4.1.2.2.2. Build and Install kernel 4.19 4.1.2.2.3. Install OPAE in kernel 4.19
5. Identify the Intel® MAX® 10 BMC Version x
5.1. FPGA Factory Image Overview
6. Intel XL710 Driver Installation and Firmware Update x
6.1. Installing the Intel XL710 Driver 6.2. Updating the Intel XL710 Firmware
8. OPAE Tools x
8.1. Using fpgasupdate 8.2. Using fpgainfo 8.3. Test PCIe and External Memories with fpgabist 8.4. Test Network Loopback using fpgadiag
10. Configuring Ethernet Interfaces x
10.1. Modifying the Interface Maximum Transmission Unit (MTU) Size 10.2. Setting Forward Error Correction (FEC) Mode 10.3. Ethernet Pause Flow Control 10.4. Get Link Statistics 10.5. Ethernet Link Status
11. Testing Network Loopback Using Data Plane Development Kit (DPDK) x
11.1. Test Using an External Traffic Generator 11.2. Revert Back from DPDK to OPAE
12. Graceful Shutdown x
12.1. Using OPAE
13. Single Event Upset (SEU) x
13.1. OPAE Handling of SEU
A. Troubleshooting x
A.1. If OPAE installation verification fails, how to install OPAE manually?
B. fpgabist Sample Output x
B.1. For 4x25G Configuration B.2. For 2x2x25G Configuration
1. About this Document
2. System Requirements
3. Hardware Installation
4. Installing the OPAE Software
5. Identify the Intel® MAX® 10 BMC Version
6. Intel XL710 Driver Installation and Firmware Update
7. Updating the Retimer Firmware
8. OPAE Tools
9. Sample Test: Native Loopback
10. Configuring Ethernet Interfaces
11. Testing Network Loopback Using Data Plane Development Kit (DPDK)
12. Graceful Shutdown
13. Single Event Upset (SEU)
14. Document Revision History for Intel Acceleration Stack User Guide: Intel® FPGA PAC N3000-N/2
A. Troubleshooting
B. fpgabist Sample Output

5.1. FPGA Factory Image Overview

The Intel® FPGA PAC N3000-N/2 has an on-board flash with two partitions (user and factory) for storing two FPGA image files known as user image and factory image. A new Intel® FPGA PAC N3000-N/2 is provided with the 2x2x25G image in factory partition and 4x25G image in user partition.

When the image in the user partition fails to load, the Intel® FPGA PAC N3000-N/2 reverts back and boots from factory partition. This factory image loaded into the user partition provides basic functionality to demonstrate all the interfaces including Ethernet and external memory interfaces.

The typical use case is a specific workload (for example: FLEXRan, ipSEC, vBNG, etc.) is loaded into the user partition. When the Intel® FPGA PAC N3000-N/2 is power cycled with a RSU command or a server power cycle, the user partition image is loaded into the Intel® Arria® 10 FPGA. The ability to load application specific images is a key benefit of the Intel® FPGA PAC N3000-N/2.

The factory image includes the following Intellectual Property (IP) to support in the development of Accelerator Function (AF):
  • The PCIe IP core
  • The Core Cache Interface protocol (CCI-P) fabric
  • DDR4 memory interface controller IP
  • QDR4 memory interface controller IP
  • 25 and 40 GbE physical interface and MACs with pass-through connectivity between Intel® Ethernet Connection C827 Retimer and Intel® Ethernet Controller XL710-BM2
  • FPGA Management Engine (FME)
  • Nios® core to configure the Intel Ethernet Connection C827 Retimers
Figure 8. Example: Factory Image for 2x2x25G
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