Intel® Acceleration Stack User Guide: Intel® FPGA Programmable Acceleration Card N3000-N/2

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ID 683362
Date 11/01/2021
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. System Requirements 3. Hardware Installation 4. Installing the OPAE Software 5. Identify the Intel® MAX® 10 BMC Version 6. Intel XL710 Driver Installation and Firmware Update 7. Updating the Retimer Firmware 8. OPAE Tools 9. Sample Test: Native Loopback 10. Configuring Ethernet Interfaces 11. Testing Network Loopback Using Data Plane Development Kit (DPDK) 12. Graceful Shutdown 13. Single Event Upset (SEU) 14. Document Revision History for Intel Acceleration Stack User Guide: Intel® FPGA PAC N3000-N/2 A. Troubleshooting B. fpgabist Sample Output
1. About this Document x
1.1. Acronym List
3. Hardware Installation x
3.1. Installing the Intel® FPGA PAC N3000-N/2
4. Installing the OPAE Software x
4.1. Install the Release Package
4.1. Install the Release Package x
4.1.1. Remove Previous OPAE Packages 4.1.2. Install the Acceleration Stack for Runtime 4.1.3. Install the Acceleration Stack for Development 4.1.4. Verify the OPAE Installation
4.1.2. Install the Acceleration Stack for Runtime x
4.1.2.1. For RHEL 4.1.2.2. For CentOS
4.1.2.2. For CentOS x
4.1.2.2.1. Download kernel 4.19 4.1.2.2.2. Build and Install kernel 4.19 4.1.2.2.3. Install OPAE in kernel 4.19
5. Identify the Intel® MAX® 10 BMC Version x
5.1. FPGA Factory Image Overview
6. Intel XL710 Driver Installation and Firmware Update x
6.1. Installing the Intel XL710 Driver 6.2. Updating the Intel XL710 Firmware
8. OPAE Tools x
8.1. Using fpgasupdate 8.2. Using fpgainfo 8.3. Test PCIe and External Memories with fpgabist 8.4. Test Network Loopback using fpgadiag
10. Configuring Ethernet Interfaces x
10.1. Modifying the Interface Maximum Transmission Unit (MTU) Size 10.2. Setting Forward Error Correction (FEC) Mode 10.3. Ethernet Pause Flow Control 10.4. Get Link Statistics 10.5. Ethernet Link Status
11. Testing Network Loopback Using Data Plane Development Kit (DPDK) x
11.1. Test Using an External Traffic Generator 11.2. Revert Back from DPDK to OPAE
12. Graceful Shutdown x
12.1. Using OPAE
13. Single Event Upset (SEU) x
13.1. OPAE Handling of SEU
A. Troubleshooting x
A.1. If OPAE installation verification fails, how to install OPAE manually?
B. fpgabist Sample Output x
B.1. For 4x25G Configuration B.2. For 2x2x25G Configuration
1. About this Document
2. System Requirements
3. Hardware Installation
4. Installing the OPAE Software
5. Identify the Intel® MAX® 10 BMC Version
6. Intel XL710 Driver Installation and Firmware Update
7. Updating the Retimer Firmware
8. OPAE Tools
9. Sample Test: Native Loopback
10. Configuring Ethernet Interfaces
11. Testing Network Loopback Using Data Plane Development Kit (DPDK)
12. Graceful Shutdown
13. Single Event Upset (SEU)
14. Document Revision History for Intel Acceleration Stack User Guide: Intel® FPGA PAC N3000-N/2
A. Troubleshooting
B. fpgabist Sample Output

10.5. Ethernet Link Status

The external Ethernet link is connected directly to the retimer device. The link status of the external Ethernet link is obtained from the retimer. The Intel® Arria® 10 FPGA and Intel XL710 device have status indications for Ethernet link status, however these are status of internal links between components.

You must obtained the Ethernet link status from the Retimers. You can obtain the Ethernet link status either using the OPAE fpgainfo phy command or using the following sysfs node which can be read for link status: 
$ cat /sys/bus/spi/drivers/intel-max10/spi0.0/pkvl/status
0xf
If your server has more than one Intel® FPGA PAC N3000-N/2 installed, then the following sysfs node must correspond to the desired Intel® FPGA PAC N3000-N/2. 
 /sys/bus/spi/drivers/intel-max10/spi<X>.0
Use the PCIe B:D.F of the desired Intel® FPGA PAC N3000-N/2 to determine the proper value of <X>. The value returned from this sysfs node is a bit level representation of link status where 1 corresponds to link up and 0 is link down.
  • Bits [0:3] corresponds to links 0-3 of QSFP A
  • Bits [4:7] corresponds to links 0-3 of QSFP B
For example, consider a returned value of 0x33:
QSFP Link 3 Link 2 Link 1 Link 0
QSFP A 0 = Link Down 0 = Link Down 1 = Link Up 1 = Link Up
QSFP B 0 = Link Down 0 = Link Down 1 = Link Up 1 = Link Up

For 4x25G network configuration, only QSFP A is used and links 0-3 are valid. For 2x2x25G network configuration, both QSFP A and B are used, however only links 1 and 0 are valid.

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