13.1.10.3. NCO Block Frequency Hopping

DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

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Date 6/20/2022

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13.1.10.3. NCO Block Frequency Hopping

Use the NCO block to configure multiple banks of predefined frequencies for frequency hopping. If you specify a matrix comprising multiple rows of vectors as the Phase Increment and Inversion values, DSP Builder configures the NCO for multiple banks and defines the number of banks by the number of rows of vectors specified by inputs to the Phase Increment and Inversion parameter. A bank input and b output are automatically added to the NCO block. It also allocates phase increment memory registers for the multiple banks of frequencies automatically.

You can use the Avalon-MM interface to access (read or write) the phase increment memory registers in the same way as for a single bank with the register address for the ith bank frequencies starting from:

<base address> + (i – 1) × <number of registers per value> × <number of channels>.

You can use the bank input as the index to switch the generated sinusoidal waves to the specified set (bank) of predefined frequencies.

Note: Ensure you constrain the bank input to the range (0 .. <number of banks> – 1). You can expect unreliable outputs from the NCO block if the bank input exceeds the number of banks.

When using an Avalon-MM interface to access (read or write) the phase increment memory registers, ensure that you only write to the inactive banks (banks which are not equal to the index specified by the input bank port). The dual-port memory that the NCO block uses is in DONT_CARE mode when reading and writing to the same address. The NCO block uses the active bank to read the phase increment value. Writing to the active bank may cause unreliable values to read out and the active bank may pass out unexpected sinusoidal signals through the memory interface.

The read data, from the address to which you write the new values to, may also be unreliable because of the memory type that the NCO block uses. Only use read data from banks where they do not write at the same time.

The Results tab shows the implications of your parameter settings.

Table 50. Results Tab Parameters for the NCO Block
Parameter	Description
Expected SFDR	The SFDR in decibels relative to the carrier (dBc): (Output Data Type Width) × 20 × log₁₀(2).
Accumulator precision	Accumulator precision in Hz: 10⁶ × (output rate) / 2^{(accumulator width in bits+1)}.
Frequency	Frequency in MHz: (output rate) × (phase increment and inversion) / 2^{(accumulator width in bits)}.
# outputs per cycle	The number of outputs per cycle is the width of the vector of output signals: physical channels out = ceil(length(phase increment and inversion)) / ((system clock frequency) / (output rate)))
log2 of look-up table	The number of address bits in the internal look-up tables.

Table 51. Port Interface for the NCO Block
Signal	Direction	Description
chan	Input	Indicates the channel. If `v` is high, `chan` indicates which channel the data corresponds to.
v	Input	Indicates validity. If `v` is high, new data generates.
phase	Input	Specifies the phase offset. The size of this port should match the wire count of the NCO. The number of sines/cosines per cycle is limited to 1–16 outputs. Use multiple NCO blocks if more outputs are required.
sync	Input	Specifies the phase synchronization. The size of this port should match the wire count of the NCO output. When asserted, the phase offsets of all channels synchronize to the phase inputs. This signal has no effect to the phase increment and inversion registers. When you use this signal, you may need to initialize the offsets upon system power-up or reset. The number of sines/cosines per cycle is limited to 1–16 outputs. Use multiple NCO blocks if more outputs are required.
bank	Input	This input is available when you specify a matrix of predefined vectors for the phase increment values. You can use this input to switch to the bank of predefined frequencies.
data	Input	The data port has unsigned integers with a width equal to the width of the accumulator plus two for the inversion bits.
address	Input	Only available when you turn on Expose Avalonmemory-mapped Agent in Simulink. The address port is the same width as the system address width that you configure in the DSP Builder > Avalon Interfaces > Avalon memory-mapped Agent menu. Also the base address is the same.
write	Input	Deassert the write port to make a read occur.
sin	Output	The sine data output from the block. If you request more channels than can fit on a single bus, this signal is a vector. The width in bits is a function of the input width in bits and the parameterization.
cos	Output	The cosine data output from the block. If you request more channels than can fit on a single bus, this signal is vector. The width in bits is a function of the input width in bits and the parameterization. The number of sines/cosines per cycle is limited to 1–16 outputs. Use multiple NCO blocks if more outputs are required.
v	Output	Indicates validity of the data output signals.
c	Output	Indicates channel of the data output signals.
b	Output	Indicates the bank that the output signals use. This output is available when you specify a matrix of predefined vectors for the phase increment values.
readdata	Output	The data port has unsigned integers with a width equal to the width of the accumulator plus two for the inversion bits.
valid	Output	Indicates a valid output.

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DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

13.1.10.3. NCO Block Frequency Hopping