Arria® 10 Device Overview

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ID 683332
Date 2/14/2022
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Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Overview x
Key Advantages of Intel® Arria® 10 Devices Summary of Intel® Arria® 10 Features Intel® Arria® 10 Device Variants and Packages I/O Vertical Migration for Intel® Arria® 10 Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O External Memory Interface PCIe Gen1, Gen2, and Gen3 Hard IP Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet Low Power Serial Transceivers SoC with Hard Processor System Dynamic and Partial Reconfiguration Enhanced Configuration and Configuration via Protocol SEU Error Detection and Correction Power Management Incremental Compilation Document Revision History for Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Variants and Packages x
Intel® Arria® 10 GX Intel® Arria® 10 GT Intel® Arria® 10 SX
Intel® Arria® 10 GX x
Available Options Maximum Resources Package Plan
Intel® Arria® 10 GT x
Available Options Maximum Resources Package Plan
Intel® Arria® 10 SX x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Intel® Arria® 10 Devices Embedded Memory Configurations for Single-port Mode
Clock Networks and PLL Clock Sources x
Clock Networks Fractional Synthesis and I/O PLLs
Fractional Synthesis and I/O PLLs x
Fractional Synthesis PLLs I/O PLLs
External Memory Interface x
Memory Standards Supported by Intel® Arria® 10 Devices
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet x
Interlaken Support 10 Gbps Ethernet Support
Low Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
PCS Features x
PCS Protocol Support
SoC with Hard Processor System x
Key Advantages of 20-nm HPS Features of the HPS FPGA Configuration and HPS Booting Hardware and Software Development
Features of the HPS x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic and Partial Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Intel® Arria® 10 Device Overview

SoC with Hard Processor System

Each SoC device combines an FPGA fabric and a hard processor system (HPS) in a single device. This combination delivers the flexibility of programmable logic with the power and cost savings of hard IP in these ways:

  • Reduces board space, system power, and bill of materials cost by eliminating a discrete embedded processor
  • Allows you to differentiate the end product in both hardware and software, and to support virtually any interface standard
  • Extends the product life and revenue through in-field hardware and software updates
Figure 9. HPS Block DiagramThis figure shows a block diagram of the HPS with the dual ARM Cortex-A9 MPCore processor.



Section Content
Key Advantages of 20-nm HPS
Features of the HPS
FPGA Configuration and HPS Booting
Hardware and Software Development

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